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Datasheet File OCR Text:

ST10F272M
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Preliminary Data
Features
16-bit CPU with DSP functions - 50ns instruction cycle time at 40 MHz max CPU clock - Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator - Enhanced boolean bit manipulations - Single-cycle context switching support On-chip memories - 256 Kbyte Flash memory (32-bit fetch) - Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles. - Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C) - 2 Kbyte internal RAM (IRAM) - 18 Kbyte extension RAM (XRAM) - Programmable external bus configuration & characteristics for different address ranges - 5 programmable chip-select signals - Hold-acknowledge bus arbitration support Interrupt - 8-channel peripheral event controller for single cycle interrupt driven data transfer - 16-priority-level interrupt system with 56 sources, sampling rate down to 25ns Timers - 2 multi-functional general purpose timer units with 5 timers Two 16-channel capture / compare units Serial channels - 2 synch. / asynch. serial channels - 2 high-speed synchronous channels - One I2C standard interface
PQFP144 (28 x 28 x 3.4mm) LQFP144 (20 x 20 x 1.4mm) (Plastic Quad Flat Package) (Low Profile Quad Flat Package)
24-channel A/D converter - 16-channel 10-bit, accuracy +/-2LSB - 8-channel 10-bit, accuracy +/-5LSB - 4.85 s minimum conversion time 4-channel PWM unit + 4-channel XPWM 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version) Fail-safe protection - Programmable watchdog timer - Oscillator watchdog On-chip bootstrap loader Clock generation - On-chip PLL with 4 to 8 MHz oscillator - Direct or prescaled clock input Real time clock and 32 kHz on-chip oscillator Up to 111 general purpose I/O lines - Individually programmable as input, output or special function - Programmable threshold (hysteresis) Idle, power-down and stand-by modes Single voltage supply: 5V 10% (embedded regulator for 1.8V core supply) Temperature range: -40 to +125C

May 2007
Rev 1
1/176
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
ST10F272M
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Special characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1 1.2.2 1.2.1 XPeripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.2 Improved supply ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 3 4 5
Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 5.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 5.2.2 5.2.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 5.4
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11 Flash control register 0 low (FCR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash control register 0 high (FCR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 1 low (FCR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash control register 1 high (FCR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash data register 0 low (FDR0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 0 high (FDR0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 1 low (FDR1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash data register 1 high (FDR1H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register low (FARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register high (FARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash error register (FER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5
Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.1 5.5.2 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash non-volatile write protection I register (FNVWPIR) . . . . . . . . . . . 35
2/9
ST10F272M 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.5.8 5.5.9
Contents Flash non-volatile access protection register 0 (FNVAPR0) . . . . . . . . . 36 Flash non-volatile access protection register 1 low (FNVAPR1L) . . . . . 36 Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 37 XBus Flash volatile temporary access unprotection register (XFVTAUR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6 5.7
Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6
Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 6.2 6.3 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 43 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 44
6.3.1 6.3.2 6.3.3 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7
Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 7.2 7.3 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8 9
External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1 9.2 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 11
Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 11.2 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12
PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3/9
Contents
ST10F272M
13
Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.1 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 I/O's special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.2.1 13.2.2 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.3
Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14 15
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.1 15.2 15.3 15.4 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 68 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 69
16 17
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.1 17.2 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.2.1 17.2.2 17.2.3 Single CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Multiple CAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
18 19 20
Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20.1 20.2 20.3 20.4 20.5 20.6 20.7 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4/9
ST10F272M
Contents
20.8 20.9
Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
21
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.1 21.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.2.1 21.2.2 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.3
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.3.1 21.3.2 21.3.3 21.3.4 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22 23
Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23.1 23.2 23.3 23.4 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
24
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
24.1 24.2 24.3 24.4 24.5 24.6 24.7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
24.7.1 24.7.2 24.7.3 24.7.4 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
24.8
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5/9
Contents 24.8.2 24.8.3 24.8.4 24.8.5 24.8.6 24.8.7 24.8.8 24.8.9
ST10F272M Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
24.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 24.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 24.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 24.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 24.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 24.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 166
25 26 27
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6/9
ST10F272M Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Address space reserved for the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Flash modules sectorization (Read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash modules sectorization (Write operations or with ROMS1 = `1' or BootStrap mode) . 26 Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Banks (BxS) and sectors (BxFy) status bits meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non-volatile access protection register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 XBus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 37 Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ST10F272M boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 57 GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 58 GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 60 PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 62 ASC asynchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . 68 ASC synchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . . 69 Synchronous baudrate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . 70 WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 100 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 List of Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 IDMANUF register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDCHIP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDMEM register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDPROG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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ST10F272M Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 PLL characteristics (VDD = 5V 10%, VSS = 0V, TA = -40 to +125C) . . . . . . . . . . . . . . 147 Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 32 kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 149 External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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ST10F272M Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ST10F272M on-chip memory mapping (ROMEN = 1 / XADRS = 800Bh - Reset value) . . 24 Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Write operation control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 73 Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 73 Connection to two different CAN buses (for example, gateway application) . . . . . . . . . . . 74 Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 74 Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . . 94 Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . 97 Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . 98 PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 101 External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 129 A/D conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ST10F272M PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 153 External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 154 External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 155
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ST10F272M Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 156 External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 159 External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE . . . . . 160 External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 161 External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 162 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP144 mechanical data and package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
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ST10F272M
Introduction
1
1.1
Introduction
Description
The ST10F272M device is a new derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F272M combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F272M is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V. The ST10F272M is an optimized version of the ST10F272E, upward compatible with the following set of differences:

Maximum CPU frequency is 40 MHz Reduced range for the Standby Voltage: VStby must be in the range of 4.5 to 5.5V. Identification registers: the IDMEM register reflects the Flash type difference and can be used to differentiate the two devices by software Improved EMC behavior thanks to the introduction of an internal RC filter on the 5V for the ballast transistors
1.2
1.2.1
Special characteristics
1.2.1 XPeripheral clock gating
This new feature have been implemented on the ST10F272M: Once the EINIT instruction has been executed, only the XPeripherals enabled in the XPERCON register will be clocked. The new feature allows to reduce the power consumption and also should improve the emissions as it avoids to propagate useless clock signals across the device.
1.2.2
1.2.2 Improved supply ring
An RC filter has been introduced in the 5V power supply ring of the ballast transistor. In addition, the supply rings for the internal voltage regulators and the IOs have been split. These two modifications should improve the behavior of the device regarding conducted emissions.
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Introduction Figure 1. Logic symbol
ST10F272M
V18 VDD VSS XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT VAREF VAGND NMI EA / VSTBY READY ALE RD WR / WRL Port 5 16-bit Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit ST10F272M Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD
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ST10F272M
Pin data
2
Pin data
Figure 2. Pin configuration (top view)
XTAL4 XTAL3 NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7 / A15 / CC27I P1H.6 / A14 / CC26I P1H.5 / A13 / CC25I P1H.4 / A12 / CC24I P1H.3 / A11 P1H.2 / A10 P1H.1 / A9 P1H.0 / A8 VSS VDD P1L.7 / A7 / AN23 P1L.6 / A6 / AN22 P1L.5 / A5 / AN21 P1L.4 / A4 / AN20 P1L.3 / A3 / AN19 P1L.2 / A2 / AN18 P1L.1 / A1 / AN17 P1L.0 / A0 / AN16 P0H.7 / AD15 P0H.6 / AD14 P0H.5 / AD13 P0H.4 / AD12 P0H.3 / AD11 P0H.2 / AD10 P0H.1 / AD9 VSS VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / MRST1 P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO P8.4 / CC20IO P8.5 / CC21IO P8.6 / RxD1 / CC22IO P8.7 / TxD1 / CC23IO VDD VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3 P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ST10F272M
P0H.0 / AD8 P0L.7 / AD7 P0L.6 / AD6 P0L.5 / AD5 P0L.4 / AD4 P0L.3 / AD3 P0L.2 / AD2 P0L.1 / AD1 P0L.0 / AD0 EA / VSTBY ALE READY WR/WRL RD VSS VDD P4.7 / A23 / CAN2_TxD / SDA P4.6 / A22 / CAN1_TxD / CAN2_TxD P4.5 / A21 / CAN1_RxD / CAN2_RxD P4.4 / A20 / CAN2_RxD / SCL P4.3 / A19 P4.2 / A18 P4.1 / A17 P4.0 / A16 RPD VSS VDD P3.15 / CLKOUT P3.13 / SCLK0 P3.12 / BHE / WRH P3.11 / RxD0 P3.10 / TxD0 P3.9 / MTSR0 P3.8 / MRST0 P3.7 / T2IN P3.6 / T3IN
VAREF VAGND P5.10 / AN10 / T6EUD P5.11 / AN11 / T5EUD P5.12 / AN12 / T6IN P5.13 / AN13 / T5IN P5.14 / AN14 / T4EUD P5.15 / AN15 / T2EUD VSS VDD P2.0 / CC0IO P2.1 / CC1IO P2.2 / CC2IO P2.3 / CC3IO P2.4 / CC4IO P2.5 / CC5IO P2.6 / CC6IO P2.7 / CC7IO VSS V18 P2.8 / CC8IO / EX0IN P2.9 / CC9IO / EX1IN P2.10 / CC10IO / EX2IN P2.11 / CC11IO / EX3IN P2.12 / CC12IO / EX4IN P2.13 / CC13IO / EX5IN P2.14 / CC14IO / EX6IN P2.15 / CC15IO / EX7IN / T7IN P3.0 / T0IN P3.1 / T6OUT P3.2 / CAPIN P3.3 / T3OUT P3.4 / T3EUD P3.5 / T4IN VSS VDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
13/176
Pin data Table 1.
Symbol
ST10F272M Pin description
Pin Type Function 8-bit bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 CS0 ... CS4 HOLD SCLK1 P6.6 HLDA MTSR1 P6.7 BREQ MRST1 Chip select 0 output ... Chip select 4 output External master hold request input SSC1: master clock output / slave clock input Hold acknowledge output SSC1: master-transmitter / slave-receiver O/I Bus request output SSC1: master-receiver / slave-transmitter I/O
1-8
I/O
1 ... P6.0 - P6.7 5 6
O ... O I I/O O
7 I/O O 8 I/O 8-bit bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions: P8.0 CC16IO XPWM0 ... P8.3 ... CC19IO XPWM0 P8.4 P8.5 P8.6 CC20IO CC21IO CC22IO RxD1 P8.7 CC23IO TxD1 CAPCOM2: CC16 capture input / compare output PWM1: channel 0 output ... CAPCOM2: CC19 capture input / compare output PWM1: channel 3 output CAPCOM2: CC20 capture input / compare output CAPCOM2: CC21 capture input / compare output CAPCOM2: CC22 capture input / compare output ASC1: Data input (Asynchronous) or I/O (Synchronous) CAPCOM2: CC23 capture input / compare output ASC1: Clock / Data output (Asynchronous/Synchronous)
9-16
I/O
I/O 9 O ... P8.0 - P8.7 12 O 13 14 15 I/O I/O 16 O I/O I/O I/O ... I/O
14/176
ST10F272M Table 1.
Symbol
Pin data Pin description (continued)
Pin Type Function 8-bit bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions: P7.0 ... P7.3 P7.4 ... P7.7 POUT0 ... POUT3 CC28IO ... CC31IO PWM0: channel 0 output ... PWM0: channel 3 output CAPCOM2: CC28 capture input / compare output ... CAPCOM2: CC31 capture input / compare output
19-26
I/O
19 P7.0 - P7.7 ... 22 23 ... 26
O ... O I/O ... I/O
27-36 39-44
I I
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs. The input threshold of Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2: timer T6 external up/down control input GPT2: timer T5 external up/down control input GPT2: timer T6 count input GPT2: timer T5 count input GPT1: timer T4 external up/down control input GPT1: timer T2 external up/down control input
P5.0 - P5.9 P5.10 - P5.15
39 40 41 42 43 44
I I I I I I
47-54 57-64
I/O
16-bit bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions: P2.0 ... P2.7 P2.8 CC0IO ... CC7IO CC8IO EX0IN ... P2.15 ... CC15IO EX7IN T7IN CAPCOM: CC0 capture input/compare output ... CAPCOM: CC7 capture input/compare output CAPCOM: CC8 capture input/compare output Fast external interrupt 0 input ... CAPCOM: CC15 capture input/compare output Fast external interrupt 7 input CAPCOM2: timer T7 count input
47 ... P2.0 - P2.7 P2.8 - P2.15 54 57
I/O ... I/O I/O I
... 64
... I/O I I
15/176
Pin data Table 1.
Symbol
ST10F272M Pin description (continued)
Pin 65-70, 73-80, 81 65 66 67 68 69 Type I/O I/O I/O I O I O I I I I I/O I/O O I/O O Function 15-bit (P3.14 is missing) bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or CMOS). The following Port 3 pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST0 MTSR0 TxD0 RxD0 BHE WRH 80 81 I/O O P3.13 P3.15 SCLK0 CLKOUT CAPCOM1: timer T0 count input GPT2: timer T6 toggle latch output GPT2: register CAPREL capture input GPT1: timer T3 toggle latch output GPT1: timer T3 external up/down control input GPT1; timer T4 input for count/gate/reload/capture GPT1: timer T3 count/gate input GPT1: timer T2 input for count/gate/reload / capture SSC0: master-receiver/slave-transmitter I/O SSC0: master-transmitter/slave-receiver O/I ASC0: clock / data output (asynchronous/synchronous) ASC0: data input (asynchronous) or I/O (synchronous) External memory high byte enable signal External memory high byte write strobe SSC0: master clock output / slave clock input System clock output (programmable divider on CPU clock)
P3.0 - P3.5 P3.6 - P3.13, P3.15
70 73 74 75 76 77 78 79
16/176
ST10F272M Table 1.
Symbol
Pin data Pin description (continued)
Pin Type Function Port 4 is an 8-bit bidirectional I/O port. It is bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 P4.1 P4.2 P4.3 A16 A17 A18 A19 A20 P4.4 CAN2_RxD SCL A21 P4.5 CAN1_RxD CAN2_RxD A22 P4.6 CAN1_TxD CAN2_TxD A23 P4.7 CAN2_TxD SDA Segment address line Segment address line Segment address line Segment address line Segment address line CAN2: receive data input I2C Interface: serial clock Segment address line CAN1: receive data input CAN2: receive data input Segment address line CAN1: transmit data output CAN2: transmit data output Most significant segment address line CAN2: transmit data output I2C Interface: serial data
85-92
I/O
85 86 87 88
O O O O O
P4.0 - P4.7
89
I I/O O
90
I I O
91
O O O
92
O I/O
RD
95
O
External memory read strobe. RD is activated for every external instruction or data read access. External memory write strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level. Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.
WR/WRL
96
O
READY/ READY
97
I
ALE
98
O
17/176
Pin data Table 1.
Symbol
ST10F272M Pin description (continued)
Pin Type Function External access enable pin. A low level applied to this pin during and after Reset forces the ST10F272M to start the program from the external memory space. A high level forces ST10F272M to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F272M under reset and main VDD turned off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5V. In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable VDD guarantees the proper biasing of all those modules. Two 8-bit bidirectional I/O ports P0L and P0H, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes
EA / VSTBY
99
I
P0L.0 - P0L.7, 100-107, P0H.0, 108, P0H.1 - P0H.7 111-117
I/O
Data path width P0L.0 - P0L.7: P0H.0 - P0H.7:
8-bit D0 - D7 I/O
16-bit D0 - D7 D8 - D15
Multiplexed bus modes Data path width P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit AD0 - AD7
A8 - A15
16-bit AD0 - AD7
AD8 - AD15
118-125 128-135 P1L.0 - P1L.7, P1H.0 - P1H.7
I/O
Two 8-bit bidirectional I/O ports P1L and P1H, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: If at least BUSCONx is configured such that the demultiplexed mode is selected, the pins of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to eight) analog input channels for the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function has a higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions: P1H.4 P1H.5 P1H.6 P1H.7 XTAL1 CC24IO CC25IO CC26IO CC27IO CAPCOM2: CC24 capture input CAPCOM2: CC25 capture input CAPCOM2: CC26 capture input CAPCOM2: CC27 capture input
132 133 134 135 XTAL1 138
I I I I I
Main oscillator amplifier circuit and/or external clock input
18/176
ST10F272M Table 1.
Symbol XTAL2
Pin data Pin description (continued)
Pin 137 Type O XTAL2 Function Main oscillator amplifier circuit output
To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed. XTAL3 XTAL4 143 144 I O XTAL3 XTAL4 32 kHz oscillator amplifier circuit input 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 must be tied to ground while XTAL4 has to be left open. Additionally, bit OFF32 in RTCCON register must be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source. Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F272M. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power-down) instruction is executed, the NMI pin must be low in order to force the ST10F272M to go into power-down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. A/D converter reference voltage and analog supply A/D converter reference and analog ground Timing pin for the return from interruptible power-down mode and synchronous / asynchronous reset selection. Digital supply voltage = +5V during normal operation, idle and power-down modes. It can be turned off when Stand-by RAM mode is selected.
RSTIN
140
I
RSTOUT
141
O
NMI
142
I
VAREF VAGND RPD
37 38 84 17, 46, 72,82,93 , 109, 126, 136 18,45, 55,71, 83,94, 110, 127, 139 56
-
VDD
-
VSS
-
Digital ground
V18
-
1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest VSS pin.
19/176
Functional description
ST10F272M
3
Functional description
The architecture of the ST10F272M combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F272M. Figure 3. Block diagram
16 IFlash 256K 32 CPU-Core and MAC Unit 16 IRAM 2K
XRAM1 16 2K (PEC) XRAM2 16 16K (STBY) 16 XRTC 16 XI2C 16 XCAN1 16 XCAN2 16 XSSC
Watchdog 16 16 16 XPWM 16 XASC Interrupt Controller PEC Oscillator 32 kHz Oscillator PLL 5V-1.8V Voltage Regulator
Port 0
16
GPT1 / GPT2
External Bus Controller
CAPCOM2
Port 1
Port 4
8
BRG
BRG
Port 6 8
Port 5 16
Port 3 15
Port 7 8
Port 8 8
20/176
Port 2
16
CAPCOM1
10-bit ADC
ASC0
SSC0
PWM
16
ST10F272M
Memory organization
4
Memory organization
The memory space of the ST10F272M is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed Bytewise or Wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF (8 Kbytes) appears at address 00'0000h: refer to Chapter 5: Internal Flash memory on page 25 for more details on memory mapping in boot mode. The summary of address range for IFlash is the following: Table 2. Summary of IFlash address range
Blocks B0TF B0F0 B0F1 B0F2 B0F3 B0F4 B0F5 B0F6 B0F7 User mode Not visible 00'0000h - 00'1FFFh 00'2000h - 00'3FFFh 00'4000h - 00'5FFFh 00'6000h - 00'7FFFh 01'8000h - 01'FFFFh 02'0000h - 02'FFFFh 03'0000h - 03'FFFFh 04'0000h - 04'FFFFh Size (bytes) 8K 8K 8K 8K 8K 32K 64K 64K 64K
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) and / or Bytewide (RL0, RH0, ..., RL7, RH7) general purpose registers group. XRAM: 16K + 2K bytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second 16 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (50ns access at 40 MHz CPU clock). Byte and Word accesses are possible. The XRAM1 address range is 00'E000h - 00'E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any access in the address range 00'E000h - 00'E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.
21/176
Memory organization
ST10F272M
After reset, the XRAM2 address range is 09'0000h - 09'3FFFh and is mirrored every 16 Kbyte boundary until 0F'FFFFh. XRAM2 also represents the Stand-by RAM, which can be maintained biased through EA / VSTBY pin when main supply VDD is turned off. As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units. CAN1: Address range 00'EF00h - 00'EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit 0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used. CAN2: Address range 00'EE00h - 00'EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 100ns at 40 MHz CPU clock. No tri-state wait states are used. Note: If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line). RTC: Address range 00'ED00h - 00'EDFFh is reserved for the RTC Module access. The RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. PWM1: Address range 00'EC00h - 00'ECFFh is reserved for the PWM1 Module access. The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. Only word access is possible. ASC1: Address range 00'E900h - 00'E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. SSC1: Address range 00'E800h - 00'E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. I2C: Address range 00'EA00h - 00'EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word
22/176
ST10F272M
Memory organization accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. X-Miscellaneous: Address range 00'EB00h - 00'EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100ns at 40 MHz CPU clock. No tristate waitstate is used. The following set of features are provided:

CLKOUT programmable divider XBUS interrupt management registers ADC multiplexing on P1L register Port1L digital disable register for extra ADC channels CAN2 multiplexing on P4.5/P4.6 CAN1-2 main clock prescaler Main Voltage Regulator disable for power-down mode TTL / CMOS threshold selection for Port0, Port1, and Port5 Flash Temporary Unprotection
In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F272M compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-Peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 23: Register set on page 108.
XPERCON and X-Peripheral clock gating
As already mentioned, the XPERCON register must be programmed to enable the single XBus modules separately. The XPERCON is a read/write ESFR register. The new feature of Clock Gating has been implemented by means of this register: Once the EINIT instruction has been executed, all the peripherals (except RAMs and XMISC) not enabled in the XPERCON register are not be clocked. The clock gating can reduce power consumption and improve EMI when the user doesn't use all X-Peripherals. Note: When the clock has been gated in the disabled Peripherals, no Reset will be raised once the EINIT instruction has been executed.
23/176
Memory organization Figure 4.
Code Segment
FF FFFF
ST10F272M
ST10F272M on-chip memory mapping (ROMEN = 1 / XADRS = 800Bh - Reset value)
Data Page 1023 Code Segment
11 FFFF
Data Page
67 66 65 64 67
RAM / SFR (4Kbyte)
255
17
11 0000 10 FFFF
Ext. Memory
00 FFFF 00 FE00 00 FDFF
SFR
512
01 0000 00 FFFF SFR 00 FE00 00 FDFF
512
16
10 0000 0F FFFF
Ext. Memory XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 Reserved
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
IRAM
2K
15
0F 0000 0E FFFF
14
0E 0000 0D FFFF
00 F600 00 F5FF
IRAM Reserved 1K
2K
13
0D 0000 0C FFFF
00 F200 00 F1FF XADRS3 = 800Bh (512K) 00 F000 00 EFFF
ESFR XCAN1 XCAN2 XRTC XPWM XMiscellaneous XI2C XASC
XSSC
512 256 256 256 256 256 256 256 256
00 F600
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
00 F5FF
12
0C 0000 0B FFFF
Reserved
1K
11
0B 0000 0A FFFF
00 E800 00 E7FF
00 F200 00 F1FF ESFR 00 F000 00 EFFF
512
10
0A 0000 09 FFFF
XRAM1
2K
9
09 0000 08 FFFF
8
08 0000 07 FFFF
00 E000 00 DFFF
7
07 0000 06 FFFF
Reserved
30 29 28 27
6
06 0000 05 FFFF
Reserved
26 25 24 23
5
05 0000 04 FFFF
Reserved
22 21 20 19 18
4
04 0000 03 FFFF
FLASH
17 16 15
Ext. Memory
8K
3
03 0000 02 FFFF
FLASH
14 13 12 11
2
02 0000 01 FFFF
FLASH
10 9 8
FLASH Ext. Memory
7 6 5 4 3
1
01 0000 00 FFFF
Address Area, where XRAM2 is mirrored every 16 Kbytes boundary after reset Bit-addressable Memory
00 C000
0
00 0000
0
0
00 0000
Ext. Memory FLASH
2 1 0
16 MB
Flash + XRAM - 1Mbyte
Data Page 3 (Segment 0) - 16Kbyte
* The first 32K of Flash may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT). Absolute Memory Address are hexadecimal values, while Data Page Number are decimal values.
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ST10F272M
Internal Flash memory
5
5.1
Internal Flash memory
Overview
The on-chip Flash is composed of one matrix module, 256 Kbytes wide. This module is called IFlash because it is on the ST10 Internal bus. Figure 5. Flash structure
IFlash Flash Control Registers Bank 0: 256 Kbyte Program Memory + 8 Kbyte Test-Flash Control Section HV and Ref. Generator
Program/Erase Controller
I-Bus Interface
The programming operations of the Flash are managed by an embedded Flash Program/Erase Controller (FPEC). The high voltages needed for Program/Erase operations are generated internally. The Data bus is 32-bit wide for fetch accesses to IFlash, whereas it is 16-bit wide for read accesses to IFlash Control Registers. Write accesses are possible only in the IFlash Control Registers area.
5.2
5.2.1
Functional description
Structure
Table 3 below shows the address space reserved for the Flash module. Table 3. Address space reserved for the Flash module
Description IFlash sectors Reserved IBus area Registers and Flash internal reserved area Addresses 0x00 0000 to 0x04 FFFF 0x05 0000 to 0x07 FFFF 0x08 0000 to 0x08 FFFF Size 256 Kbytes 192 Kbytes 64 Kbytes
5.2.2
Modules structure
The IFlash module is composed of a bank (Bank 0) of 256 Kbytes of Program Memory divided in eight sectors (B0F0...B0F7). Bank 0 also contains a reserved sector named TestFlash.
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Internal Flash memory
ST10F272M
The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register Interface and other internal service memory space used by the Flash Program/Erase controller. The following tables show the memory mapping of the Flash when it is accessed in read mode (Table 4: Flash modules sectorization (Read operations)), and when accessed in write or erase mode (Table 5: Flash modules sectorization (Write operations or with ROMS1 = `1' or BootStrap mode)). Note: With this second mapping, the first four banks are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON register). Table 4.
Bank
Flash modules sectorization (Read operations)
Description Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) Addresses 0x0000 0000 - 0x0000 1FFF 0x0000 2000 - 0x0000 3FFF 0x0000 4000 - 0x0000 5FFF 0x0000 6000 - 0x0000 7FFF 0x0001 8000 - 0x0001 FFFF 0x0002 0000 - 0x0002 FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF Size ST10 Bus size (bytes) 8K 8K 8K 8K 32-bit (IBus) Bank 0 Flash 4 (B0F4) Bank 0 Flash 5 (B0F5) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7) 32K 64K 64K 64K
B0
Table 5.
Flash modules sectorization (Write operations or with ROMS1 = `1' or BootStrap mode)
Description Bank 0 Test-Flash (B0TF) Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Addresses 0x0000 0000 - 0x0000 1FFF 0x0001 0000 - 0x0001 1FFF 0x0001 2000 - 0x0001 3FFF 0x0001 4000 - 0x0001 5FFF 0x0001 6000 - 0x0001 7FFF 0x0001 8000 - 0x0001 FFFF 0x0002 0000 - 0x0002 FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF Size ST10 Bus size (bytes) 8K 8K 8K 8K 8K 32K 64K 64K 64K 32-bit (IBus)
Bank
B0
Bank 0 Flash 3 (B0F3) Bank 0 Flash 4 (B0F4) Bank 0 Flash 5 (B0F5) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7)
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ST10F272M
Internal Flash memory Table 5 above refers to the configuration when bit ROMS1 of SYSCON register is set. Refer to the device User Manual for more details on the memory mapping during Bootstrap mode. In particular, when Bootstrap mode is entered:

Test-Flash is seen and available for code fetches (address 00'0000h) User IFlash is only available for read and write accesses Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0. Example: In default configuration, to program address 0, the user must put the value 01'0000h in the FARL and FARH registers but to verify the content of the address 0, a read to 00'0000h must be performed. The next Table 6 shows the Control Register interface composition: This set of registers can be addressed by the CPU. Table 6.
Name FCR1-0 FDR1-0 FAR FER FNVWPIR FNVPIRMirror FNVAPR0 FNVAPR1 XFVTAUR0
Control register interface
Description Flash Control Registers 1-0 Flash Data Registers 1-0 Flash Address Registers Flash Error Register Flash Non-Volatile Protection I Register Mirror of Flash Non-Volatile Protection I Register Flash Non-Volatile Access Protection Register 0 Flash Non-Volatile Access Protection Register 1 XBus Flash Volatile Temporary Access Unprotection Register 0 Addresses 0x0008 0000 - 0x0008 0007 0x0008 0008 - 0x0008 000F 0x0008 0010 - 0x0008 0013 0x0008 0014 - 0x0008 0015 0x0008 DFB0 - 0x0008 DFB1 0x0008 DFB4 - 0x0008 DFB5 0x0008 DFB8 - 0x0008 DFB9 0x0008 DFBC - 0x0008 DFBF 0x0000 EB50 - 0x0000 EB51 Size 8 bytes 8 bytes 4 bytes 2 bytes 2 bytes 2 bytes 2 bytes 4 bytes 2 bytes
5.2.3
Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (tPD). Recovery time from Power-down mode for the Flash modules is anyway shorter than the main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.
Note:
PWRDN instruction must not be executed while a Flash program/erase operation is in progress.
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Internal Flash memory
ST10F272M
5.3
Write operation
The Flash module has one single register interface mapped in the memory space of the IBus (08'0000h - 08'0015h). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash address and data for program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8- and 16-bit instructions (since the IBUS operates in 16-bit mode for read/write accesses to data).
Note:
The register that controls the Temporary Unprotection of the Flash is located on the XBus at address 00'EB50h in the XMiscellaneous Register area. Before accessing the IFlash module (and consequently the Flash register to be used for program/erasing operations), the ROMEN bit in SYSCON register must be set.
Caution:
During a Flash write operation any attempt to read the Flash itself, that is under modification, will output invalid data (software trap 009Bh). This means that the Flash is not fetchable when a programming operation is active:The write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not possible to perform a write operation on IFlash, when fetching code from IFlash. Direct addressing is not allowed for write accesses to IFlash Control Registers.
Warning:
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated.
5.4
5.4.1
Registers description
Flash control register 0 low (FCR0L)
The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) are used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is seen by the user in Bootstrap mode only.
FCR0L (0x08 0000) 15 14 13 12 11 10 Reserved 9 8 FCR 7 6 5 4 RO 3 Reset value: 0000h 2 1 RO 0 LOCK Reserved BSY0 Res.
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ST10F272M Table 7.
Bit Name
Internal Flash memory Flash control register 0 low
Function
4
Flash Registers Access Locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write LOCK access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when the BSY0 bit is reset. Bank 0 Busy (IFlash) This bit indicates that a write operation is running on Bank 0 (IFlash). It is automatically set when bit WMS is set. Setting Protection operation sets bit BSY0 (since protection BSY0 registers are in this Block). When this bit is set, every read access to Bank 0 will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend this bit is automatically reset and the Bank returns to read mode. After a Program or Erase Resume this bit is automatically set again.
1
5.4.2
Flash control register 0 high (FCR0H)
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is seen by the user in Bootstrap mode only.
FCR0H (0x08 0002) 15
WMS
FCR 12 11
SER
Reset value: 0000h 7 6 5 4 3 2 1 0
14
SUSP
13
10
9
8
SPR
WPG DWPG
Reserved
Reserved
RW
RW
RW
RW
RW
-
RW
-
Table 8.
Bit Name
Flash control register 0 high
Function Write Mode Start This bit must be set to start every write operation in the Flash module. At the end of the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect.
15
WMS
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Internal Flash memory Table 8.
Bit Name
ST10F272M Flash control register 0 high (continued)
Function
Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank. The Suspend operation resets the Flash Bank to normal read mode (automatically resetting bit BSY0). When in Program Suspend, the Flash module accepts only the following operations: Read and Program 14 SUSP Resume. When in Erase Suspend the module accepts only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase Suspend). To resume a suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG, DWPG, SER). Note: It is forbidden to start a new Write operation with bit SUSP already set. Word Program This bit must be set to select the Word (32 bits) Program operation in the Flash module. The Word Program operation can be used to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation.
13
WPG
Double Word Program This bit must be set to select the Double Word (64 bits) Program operation in the Flash module. The Double Word Program operation can be used to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the 12 DWPG FARH/L registers, while the two Flash Data words to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation. Sector Erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase operation can be used to erase all the Flash locations to value 0xFF. From 1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to preprogram the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation. Set Protection This bit must be set to select the Set Protection operation. The Set Protection operation can be used to program 0s in place of 1s in the Flash Non-Volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range of 0x0E8FB0 to 0x08DFBF. SPR bit is automatically reset at the end of the Set Protection operation.
11
SER
8
SPR
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Internal Flash memory
5.4.3
Flash control register 1 low (FCR1L)
The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High (FCR1H), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank.
FCR1L (0x08 0004) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
Reserved -
B0F7 B0F6 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0 RS RS RS RS RS RS RS RS
Table 9.
Bit
Flash control register 1 low
Function Bank 0 IFlash Sectors 7-0 Status These bits must be set during a Sector Erase operation to select the sectors to erase in Bank 0. Moreover, during any erase operation, these bits are automatically set and give the status of the eight sectors of Bank 0 (B0F7-B0F0). The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of a Write operation if no errors are detected.
Name
7:0
B0F[7:0]
5.4.4
Flash control register 1 high (FCR1H)
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank.
FCR1H (0x08 0006) 15 14 13 12 Reserved 11 10 9 FCR 8 B0S RS 7 6 5 4 3 Reset value: 0000h 2 1 0
Reserved -
Table 10.
Bit
Flash control register 1 high
Function Bank 0 Status (IFlash) During any erase operation, this bit is automatically modified and gives the status of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of an erase operation if no errors are detected.
Name
8
B0S
During any erase operation, this bit is automatically set and gives the status of the Bank 0. The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an erase operation if no errors are detected.
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Internal Flash memory Table 11.
ERR 1 0 0
ST10F272M Banks (BxS) and sectors (BxFy) status bits meaning
B0S = 1 meaning Erase Error in Bank0 Erase Suspended in Bank0 Don't care B0Fy = 1 meaning Erase Error in Sector y of Bank0 Erase Suspended in Sector y of Bank0 Don't care
SUSP 1 0
5.4.5
Flash data register 0 low (FDR0L)
During program operations, the Flash Address Registers (FARH/L) are used to store the Flash address in which to program and the Flash Data Registers (FDR1H/L-FDR0H/L) are used to store the Flash data to program.
FDR0L (0x08 0008) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 12.
Bit
Flash data register 0 low
Function
Name
Data Input 15:0 15:0 DIN[15:0] These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.
5.4.6
Flash data register 0 high (FDR0H)
FDR0H (0x08 000A) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 13.
Bit
Flash data register 0 high
Function
Name
Data Input 31:16 15:0 DIN[31:16] These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.
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Internal Flash memory
5.4.7
Flash data register 1 low (FDR1L)
FDR1L (0x08 000C) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 14.
Bit
Flash data register 1 low
Function
Name
Data Input 15:0 15:0 DIN[15:0] These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.
5.4.8
Flash data register 1 high (FDR1H)
FDR1H (0x08 000E) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 15.
Bit
Flash data register 1 high
Function
Name
Data Input 31:16 15:0 DIN[31:16] These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection.
5.4.9
Flash address register low (FARL)
FARL (0x08 0010) 15 14 13 12 11 10 9 FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 Reserved RW RW RW RW RW RW RW RW RW RW RW RW RW RW -
Table 16.
Bit
Flash address register low
Function
Name
Address 15:2 15:2 ADD[15:2] These bits must be written with the Address of the Flash location to program in the following operations: Word Program (32-bit) and Double Word Program (64-bit). In Double Word Program bit ADD2 must be written to `0'.
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5.4.10
Flash address register high (FARH)
FARH (0x08 0012) 15 14 13 12 11 10 Reserved 9 FCR 8 7 6 5 4 3 Reset value: 0000h 2 1 0
ADD20 ADD19 ADD18 ADD17 ADD16
RW
RW
RW
RW
RW
Table 17.
Bit
Flash address register high
Function
Name
Address 20:16 4:0 ADD[20:16] These bits must be written with the Address of the Flash location to program in the following operations: Word Program and Double Word Program.
5.4.11
Flash error register (FER)
The Flash Error register, as well as all the other Flash registers, can be read only once the LOCK bit of register FCR0L is low. Nevertheless, the FER content is updated after completion of the Flash operation, that is, when BSY0 is reset. Therefore, the FER content can only be read once the LOCK and BSY0 bits are cleared.
FER (0x8 0014h) 15 14 13 12
Reserved
FCR 11 10 9 8 7 6 5 4 3
Reset value: 0000h 2 1 0
ERR
WPF RESER SEQER
Reserved
10ER PGER ERER
-
RC
RC
RC
-
RC
RC
RC
RC
Table 18.
Bit
Flash error register
Function Write Error This bit is automatically set when an error occurs during a Flash write operation or when a bad write operation setup is done. Once the error has been discovered and understood, ERR bit must be software reset. Erase Error This bit is automatically set when an Erase error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be erased. This kind of error is fatal and the sector where it occurred must be discarded. This bit has to be software reset. Program Error This bit is automatically set when a Program error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be programmed. The word where this error occurred must be discarded. This bit has to be software reset. 1 over 0 Error This bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the Protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset.
Name
0
ERR
1
ERER
2
PGER
3
10ER
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ST10F272M Table 18.
Bit
Internal Flash memory Flash error register (continued)
Function Sequence Error This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid Write Operation. In this case no Write Operation is executed. This bit has to be software reset. Resume Error This bit is automatically set when a suspended Program or Erase operation is not resumed correctly due to a protocol error. In this case the suspended operation is aborted. This bit has to be software reset. Write Protection Flag This bit is automatically set when trying to program or erase in a sector write protected. In case of multiple Sector Erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset.
Name
6
SEQER
7
RESER
8
WPF
5.5
Protection strategy
The protection bits are stored in Non-Volatile Flash cells inside IFlash module, that are read once at reset and stored in four Volatile registers. Before they are read from the NonVolatile cells, all the available protections are forced active during reset. The protections can be programmed using the Set Protection operation (see Flash Control Registers paragraph), that can be executed from all the internal or external memories except from the Flash itself. Two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. In next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well.
5.5.1
Protection registers
The four Non-Volatile Protection Registers are one time programmable for the user. One register (FNVWPIR) is used to store the Write Protection fuses respectively for each sector IFlash module. The other three Registers (FNVAPR0 and FNVAPR1L/H) are used to store the Access Protection fuses.
5.5.2
Flash non-volatile write protection I register (FNVWPIR)
FNVWPIR (0x08 DFB0) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 3 Reset value: FFFFh 2 1 0
Reserved -
W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 RW RW RW RW RW RW RW RW
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Internal Flash memory Table 19.
Bit
ST10F272M Flash non-volatile write protection I register
Function Write Protection Bank 0 / Sectors 7-0 (IFlash) These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFlash)
Name
7:0
W0P[7:0]
5.5.3
Flash non-volatile access protection register 0 (FNVAPR0)
FNVAPR0 (0x08 DFB8) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: ACFFh 3 2 1 0
Reserved -
DBGP ACCP
RW
RW
Table 20.
Bit
Flash non-volatile access protection register 0
Function Access Protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from IFlash. Debug Protection This bit, if erased at 1, can be used to by-pass all the protections using the Debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis.
Name
0
ACCP
1
DBGP
5.5.4
Flash non-volatile access protection register 1 low (FNVAPR1L)
FNVAPR1L (0x08 DFBC) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: FFFFh 3 2 1 0
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 21.
Bit
Flash non-volatile access protection register 1 low
Function
Name
Protections Disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP 15:0 PDS[15:0] is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0.
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ST10F272M
Internal Flash memory
5.5.5
Flash non-volatile access protection register 1 high (FNVAPR1H)
FNVAPR1H (0x08 DFBE) 15 14 13 12 11 10 9 NVR 8 7 6 5 4 Delivery value: FFFFh 3 2 1 0
PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 22.
Bit
Flash non-volatile access protection register 1 high
Function
Name
Protections Enable 15-0 15:0 PEN[15:0] If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0.
5.5.6
XBus Flash volatile temporary access unprotection register (XFVTAUR0)
XFVTAUR0 (0x00 EB50) 15 14 13 12 11 10 9 NVR 8 Reserved 7 6 5 4 3 Reset value: 0000h 2 1 0 TAUB RW
Table 23.
Bit
XBus Flash volatile temporary access unprotection register
Function Temporary Access Unprotection bit If this bit is set to 1, the Access Protection is temporary disabled. The fact that this bit can be written only while executing from IFlash guarantees that only a code executed in IFlash can unprotect the IFlash when it is Access Protected.
Name
0
TAUB
5.5.7
Access protection
The IFlash module has one level of access protection (access to data both in Reading and Writing). When bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at 0, the IFlash module becomes access protected (data in the IFlash module can be read only if the current execution is from the IFlash module itself). Trying to read into the access protected Flash from internal RAM or external memories will output a dummy data (software trap 009Bh). When the Flash module is protected in access, data access through PEC transfers is also forbidden. To read/write data through PEC in a protected Bank, first it is necessary to temporarily unprotect the Flash module.
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Internal Flash memory
ST10F272M
To enable Access Protection, the following sequence of operations is recommended:

execution from external memory or internal Rams program TAUB bit at 1 in XFVTAUR0 register program ACCP bit in FNVAPR0 to 0 using Set Protection operation program TAUB bit at 0 in XFVTAUR0 register Access Protection is active when both ACCP bit and TAUB bit are set to 0.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporarily unprotected (see Section 5.5.9: Temporary unprotection). Trying to write into the access protected Flash from internal RAM or external memories will be unsuccessful. Trying to read into the access protected Flash from internal RAM or external memories will output dummy data (software trap 0x009Bh). When the Flash module is protected in access, data access through PEC of a peripheral is also forbidden. To read/write data in PEC mode from/to a protected Bank, it is necessary to first temporarily unprotect the Flash module. The following table summarizes all possible Access Protection levels: In particular, it shows what is possible and not possible to do when fetching from a memory (see fetch location column) supposing all possible access protections are enabled. Table 24. Summary of access protection level
Read IFlash / Jump to IFlash Yes / Yes No / Yes No / Yes No / Yes Read XRAM or External Memory / Jump to XRAM or External Memory Yes / Yes Yes / Yes Yes / Yes Yes / Yes Read Flash registers Yes No No No Write Flash registers No No No No
Fetch location
Fetching from IFlash Fetching from IRAM Fetching from XRAM Fetching from External Memory
When the Access Protection is enabled, Flash registers can not be written, so no program/erase operation can be run on IFlash. To enable the access to registers again, the Temporary Access Unprotection procedure has to be followed (see Section 5.5.9).
5.5.8
Write protection
The Flash modules have one level of Write Protections: each Sector of each Bank of each Flash Module can be Software Write Protected by programming at 0 the related bit W0Px in FNVWPIRL register.
5.5.9
Temporary unprotection
Bits W0Px of FNVWPIRL can be temporarily unprotected by executing the Set Protection operation and by writing 1 into these bits.
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ST10F272M
Internal Flash memory To restore the write protection bits it is necessary to reset the microcontroller or to execute a Set Protection operation and write 0 into the desired bits. In reality, when a temporary write unprotection operation is executed, the corresponding volatile register is written to 1, while the non-volatile registers bits previously written to 0 (for a protection set operation), will continue to maintain the 0. For this reason, the User software must be in charge to track the current write protection status (for instance using a specific RAM area), it is not possible to deduce it by reading the non-volatile register content (a temporary unprotection cannot be detected). To temporarily unprotect the Flash when the Access Protection is active, it is necessary to set to `1' the bit TAUB in XFVTAUR0. This bit can be set to `1' only while executing from Flash: In this way only an instruction executed from Flash can unprotect the Flash itself. To restore the Access Protection, it is necessary to reset the microcontroller or to write at 0 the bit TAUB in XFVTAUR0.
5.6
Note:
Write operation examples
In the following, examples for each kind of Flash write operation are presented. The write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not possible to perform write operation in Flash while fetching code from Flash. Moreover, direct addressing is not allowed for write accesses to IFlash control registers. This means that both address and data for a writing operation must be loaded in one of ST10 GPR register (R0...R15). Write operation on IBus registers is 16 bits wide.
Example of indirect addressing mode
MOV MOV MOV RWm, #ADDRESS; RWn, #DATA; [RWm], RWn; /*Load Add in RWm*/ /*Load Data in RWn*/ /*Indirect addressing*/
Word program
Example: 32-bit Word Program of data 0xAAAAAAAA at address 0x025554 FCR0H|= FARL = FARH = FDR0L = FDR0H = FCR0H|= 0x2000; 0x5554; 0x0002; 0xAAAA; 0xAAAA; 0x8000; /*Set WPG in FCR0H*/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/
Double word program
Example: Double Word Program (64-bit) of data 0x55AA55AA at address 0x035558 and data 0xAA55AA55 at address 0x03555C in IFlash Module. FCR0H FARL FARH FDR0L |= 0x1000; = 0x5558; = 0x0003; = 0x55AA; /*Set DWPG/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/
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Internal Flash memory FDR0H FDR1L FDR1H FCR0H = = = |= 0x55AA; 0xAA55; 0xAA55; 0x8000; /*Load Data /*Load Data /*Load Data /*Operation in FDR0H*/ in FDR1L*/ in FDR1H*/ start*/
ST10F272M
Double Word Program is always performed on the Double Word aligned on an even Word: bit ADD2 of FARL is ignored.
Sector erase
Example: Sector Erase of sectors B0F1 and B0F0 of Bank 0 in IFlash Module. FCR0H FCR1L FCR0H |= 0x0800; |= 0x0003; |= 0x8000; /*Set SER in FCR0H*/ /*Set B0F1, B0F0*/ /*Operation start*/
Suspend and resume
Word Program, Double Word Program, and Sector Erase operations can be suspended in the following way: FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
Then the operation can be resumed in the following way: FCR0H FCR0H |= 0x0800; |= 0x8000; /*Set SER in FCR0H*/ /*Operation resume*/
Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set.
Set protection
Example 1: Enable Write Protection of sectors B0F3-0 of Bank 0 in IFlash module. FCR0H FARL FARH FDR0L FDR0H FCR0H |= = = = = |= 0x0100; 0xDFB4; 0x0008; 0xFFF0; 0xFFFF; 0x8000; /*Set SPR in FCR0H*/ /*Load Add of register FNVWPIR in FARL*/ /*Load Add of register FNVWPIR in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/
Example 2: Enable Access and Debug Protection. FCR0H FARL FARH FDR0L FCR0H |= = = = |= 0x0100; 0xDFB8; 0x0008; 0xFFFC; 0x8000; /*Set SPR in FCR0H*/ /*Load Add of register FNVAPR0 in FARL*/ /*Load Add of register FNVAPR0 in FARH*/ /*Load Data in FDR0L*/ /*Operation start*/
Example 3: Disable in a permanent way Access and Debug Protection. XFVTAUR0 = 0x0001; FCR0H |= 0x0100; FARL = 0xDFBC; FARH = 0x0008; FDR0L = 0xFFFE; /*Set TAUB in XFVTAUR0*/ /*Set SPR in FCR0H*/ /*Load Add of register FNVAPR1L in FARL*/ /*Load Add of register FNVAPR1L in FARH*/ /*Load Data in FDR0L for clearing PDS0*/
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ST10F272M FCR0H |= 0x8000; /*Operation start*/
Internal Flash memory
Example 4: Enable again in a permanent way Access and Debug Protection, after having disabled them. XFVTAUR0 = 0x0001; FCR0H |= 0x0100; FARL = 0xDFBC; FARH = 0x0008; FDR0H = 0xFFFE; PEN0*/ FCR0H |= 0x8000; XFVTAUR0 = 0x0000; /*Set TAUB in XFVTAUR0*/ /*Set SPR in FCR0H*/ /*Load Add register FNVAPR1H in FARL*/ /*Load Add register FNVAPR1H in FARH*/ /*Load Data in FDR0H for clearing /*Operation start*/ /*Reset TAUB in XFVTAUR0*/
Disable and re-enable of Access and Debug Protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times.
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Internal Flash memory
ST10F272M
5.7
Write operation summary
In general, each write operation is started through a sequence of three steps: 1. 2. 3. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. The second step is the definition of the Address and Data for programming or the Sectors or Banks to erase. The last instruction is used to start the write operation, by setting the start bit WMS in the FCR0.
Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. Available Flash Module Write Operations are summarized in the following Table 25. Table 25. Flash write operations
Operation Word Program (32-bit) Select bit WPG Address and data FARL/FARH FDR0L/FDR0H FARL/FARH FDR0L/FDR0H FDR1L/FDR1H FCR1L/FCR1H FDR0L/FDR0H None Start bit WMS
Double Word Program (64-bit) Sector Erase Set Protection Program/Erase Suspend
DWPG SER SPR SUSP
WMS WMS WMS None
Figure 6 shows the complete flow needed for a Write operation. Figure 6. Write operation control flow
Start Write Operation
FCR0L.LOCK == 0?
Yes
No
Write Operation finished?
(Check related busy bit) Yes No
Check Error Status Error:
Error handler, ... Re-start operation
No error:
Proceed with application
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ST10F272M
Bootstrap loader
6
Bootstrap loader
The ST10F272M implements Boot capabilities in order to:

Support bootstrap via UART or bootstrap via CAN for the standard bootstrap Support a Selective Bootstrap Loader, to manage the bootstrap sequence in a different way
6.1
Selection among user-code, standard or selective bootstrap
The boot modes are triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN pin.

Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) selects the normal mode (also called User mode) and selects the user Flash to be mapped from address 00'0000h. Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) selects ST10 standard bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read accesses). Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) activates new verifications to select which bootstrap software to execute: - - if the User mode signature in the User Flash is programmed correctly, then a software reset sequence is selected and the User code is executed; if the User mode signature is not programmed correctly in the user Flash, then the User key location is read again. Its value determines which communication channel will be enabled for bootstrapping. ST10F272M boot mode selection
P0.4 1 0 ST10 decoding User mode: User Flash mapped at 00'0000h Standard Bootstrap Loader: User Flash mapped from 00'0000h, code fetches redirected to Test-Flash at 00'0000h Selective Boot mode: User Flash mapped from 00'0000h, code fetches redirected to Test-Flash at 00'0000h (different sequence execution compared to Standard Bootstrap Loader) Reserved
Table 26.
P0.5 1 1
.
0 0
1 0
6.2
Standard bootstrap loader
After entering the standard BSL mode and the respective initialization, the ST10F272M scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line. Start condition on UART RxD: ST10F272M starts standard bootstrap loader. This bootstrap loader is identical to that of other ST10 devices (example: ST10F269, ST10F168). Valid dominant bit on CAN1 RxD: ST10F272M start bootstrapping via CAN1.
Caution:
As both UART_RxD and CAN1_RxD lines are polled to detect a start of communication, ensure a stable level on the unused channel by adding a pull-up resistor.
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Bootstrap loader
ST10F272M
6.3
6.3.1
Alternate and selective boot mode (ABM and SBM)
Activation of the ABM and SBM
Alternate boot is activated with the combination `01' on Port0L[5..4] at the rising edge of RSTIN.
6.3.2
User mode signature integrity check
The behavior of the Selective Boot mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature. This requires that users who use Selective Boot have reserved and programmed the Flash memory locations.
6.3.3
Selective boot mode
When the user signature is not correct, instead of executing the Standard Bootstrap Loader (triggered by P0L.4 low at reset), additional check is made. Depending on the value at the User key location, the following behavior occurs:

A jump is performed to the Standard Bootstrap Loader Only UART is enabled for bootstrapping Only CAN1 is enabled for bootstrapping The device enters an infinite loop
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ST10F272M
Central processing unit (CPU)
7
Central processing unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F272M's instructions can be executed in one instruction cycle which requires 50ns at 40 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
Figure 7.
CPU block diagram (MAC unit not included)
16 CPU SP STKOV STKUN 256 Kbyte Flash memory 32 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs Exec. Unit Instr. Ptr 4-Stage Pipeline MDH MDL Mul./Div.-HW Bit-Mask Gen. R15 2K Byte Internal RAM Bank n
ALU 16-Bit Barrel-Shift CP ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr.
General Purpose Registers
R0
Bank i
16
Bank 0
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Central processing unit (CPU)
ST10F272M
7.1
Multiplier-accumulator unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle. This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit. The co-processor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations. Figure 8. MAC unit architecture
Operand 1 16 Operand 2 16
GPR Pointers IDX0 Pointer IDX1 Pointer
(1)
QR0 GPR Offset Register QR1 GPR Offset Register QX0 IDX Offset Register QX1 IDX Offset Register
Concatenation 32
16 x 16 signed/unsigned Multiplier
32 Mux Sign Extend
MRW 0h 40 Repeat Unit Interrupt Controller ST10 CPU MSW
Scaler 08000h 40 40 Mux 40 0h 40 40 Mux 40
MCW
A B 40-bit Signed Arithmetic Unit 40 MAH 40 8-bit Left/Right Shifter MAL
Flags MAE Control Unit
1. Shared with standard ALU
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ST10F272M
Central processing unit (CPU)
7.2
Instruction set summary
Table 27 lists the instructions of the ST10F272M. The detailed description of each instruction can be found in the ST10 Family Programming Manual. Table 27. Standard instruction set summary
Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-/16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS
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Central processing unit (CPU) Table 27. Standard instruction set summary (continued)
Description Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack
ST10F272M
Mnemonic J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP
Bytes 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power-down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation
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ST10F272M
Central processing unit (CPU)
7.3
MAC co-processor specific instructions
Table 28 lists the MAC instructions of the ST10F272M. The detailed description of each instruction can be found in the ST10 Family Programming Manual. Note that all MAC instructions are encoded on 4 bytes. Table 28. MAC instruction set summary
Mnemonic CoABS CoADD(2) CoASHR(rnd) CoCMP CoLOAD(-,2) CoMAC(R,u,s,-,rnd) CoMACM(R)(u,s,-,rnd) CoMAX / CoMIN CoMOV CoMUL(u,s,-,rnd) CoNEG(rnd) CoNOP CoRND CoSHL / CoSHR CoSTORE CoSUB(2,R) Description Absolute Value of the Accumulator Addition Accumulator Arithmetic Shift Right & Optional Round Compare Accumulator with Operands Load Accumulator with Operands (Un)Signed/(Un)Signed Multiply-Accumulate & Optional Round (Un)Signed/(Un)Signed Multiply-Accumulate with Parallel Data Move & Optional Round Maximum / Minimum of Operands and Accumulator Memory to Memory Move (Un)Signed/(Un)Signed multiply & Optional Round Negate Accumulator & Optional Round No-Operation Round Accumulator Accumulator Logical Shift Left / Right Store a MAC Unit Register Subtraction
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External bus controller
ST10F272M
8
External bus controller
All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes:

16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input / output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to four independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these four address windows are controlled by BUSCON0. Up to five external CS signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD / HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16 Mbytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.
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ST10F272M
Interrupt system
9
Interrupt system
The interrupt response time for internal program execution is from 125ns to 300ns at 40 MHz CPU clock. The ST10F272M architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F272M has eight PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Fast external interrupts may also have interrupt sources selected from other peripherals; for example, the CANx controller receives signals (CANx_RxD) and I2C serial clock signal can be used to interrupt the system. Table 29 shows all the available ST10F272M interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Table 29. Interrupt sources
Request flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR Enable flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE Interrupt vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT Vector location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h Trap number 10h 11h 12h 13h 14h 15h
Source of interrupt or PEC service request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5
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Interrupt system Table 29. Interrupt sources (continued)
Request flag CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR Enable flag CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE Interrupt vector CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT Vector location 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00F0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h
ST10F272M
Source of interrupt or PEC service request CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5
Trap number 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h
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ST10F272M Table 29. Interrupt sources (continued)
Request flag T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable flag T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt vector T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT
Interrupt system
Source of interrupt or PEC service request GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 See Paragraph 9.1 See Paragraph 9.1 See Paragraph 9.1 See Paragraph 9.1
Vector location 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch
Trap number 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h
Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). A hardware trap will interrupt any other program execution except when another higher prioritized trap service is in progress. Hardware trap services cannot not be interrupted by a standard interrupt or by PEC interrupts.
9.1
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional XPeripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt management is proposed. In the next Figure 9, the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT). It is based on a set of 16-bit registers XIRxSEL (x = 0,1,2,3), divided in two portions each:

Byte High Byte Low
XIRxSEL[15:8] XIRxSEL[7:0]
Interrupt Enable bits Interrupt Flag bits
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique
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available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since they are masked through the enable bits), allowing an effective software management even if the related interrupt request cannot be served: A periodic polling of the flag bits may be implemented inside the user application. Figure 9. X-Interrupt basic structure
7 0
Flag[7:0] IT Source 7 IT Source 6 IT Source 5 IT Source 4 IT Source 3 IT Source 2 IT Source 1 IT Source 0 Enable[7:0]
15 8
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XPxIC.XPxIR (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
Table 30 summarizes the mapping of the different interrupt sources which shares the four Xinterrupt vectors. Table 30. X-Interrupt detailed mapping
Interrupt source CAN1 Interrupt CAN2 Interrupt I2C Receive I2C Transmit I2C Error SSC1 Receive SSC1 Transmit SSC1 Error ASC1 Receive ASC1 Transmit ASC1 Transmit Buffer x x x x x x x x x x x x x x x x x x XP0INT x x x x x x x XP1INT XP2INT XP3INT x x
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ST10F272M Table 30. X-Interrupt detailed mapping (continued)
Interrupt source ASC1 Error PLL Unlock / OWD PWM1 Channel 3...0
x
Interrupt system
XP0INT
XP1INT
XP2INT
XP3INT x
x x
9.2
Exception and error traps list
Table 31 shows all of the possible exceptions or error conditions that can arise during runtime. Table 31. Trap priorities
Trap flag Trap vector RESET RESET RESET NMI STKOF STKUF UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS NMITRAP STOTRAP STUTRAP BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP Vector location 00'0000h 00'0000h 00'0000h 00'0008h 00'0010h 00'0018h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [002Ch - 003Ch] Any 0000h - 01FCh in steps of 4h Trap number 00h 00h 00h 02h 04h 06h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] Any [00h - 7Fh] Current CPU Priority Trap priority(1) III III III II II II I I I I I I
Exception condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode MAC Interruption Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction
1. - All the class B traps have the same trap number (and vector) and the same lower priority compared to the class A traps and to the resets. - Each class A trap has a dedicated trap number (and vector). They are prioritized in the second priority level. - The resets have the highest priority level and the same trap number. - The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced.
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Capture / compare (CAPCOM) units
ST10F272M
10
Capture / compare (CAPCOM) units
The ST10F272M has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 40 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution, and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode. The input frequencies fTx, for the timer input selector Tx, are determined as a function of the CPU clocks. The timer input frequencies, resolution and periods which result from the selected prescaler option in TxI when using a 40 MHz CPU clock are listed in Table 33. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded off to three significant figures.
Table 32.
Compare modes
Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated
Compare modes Mode 0 Mode 1 Mode 2
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ST10F272M Table 32. Compare modes (continued)
Capture / compare (CAPCOM) units
Compare modes Mode 3 Double Register Mode
Function Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Table 33.
CAPCOM timer input frequencies, resolutions and periods at 40 MHz
Timer input selection TxI
fCPU = 40 MHz 000b Prescaler for
fCPU
001b 16 2.5 MHz 400ns 26.2ms
010b 32 1.25 MHz 0.8s 52.4ms
011b 64 625 kHz 1.6s 104.8 ms
100b 128 312.5 kHz 3.2s 209.7ms
101b 256 156.25 kHz 6.4s 419.4ms
110b 512 78.125 kHz 12.8s 838.9ms
111b 1024 39.1 kHz 25.6s 1.678s
8 5 MHz 200ns 13.1ms
Input frequency Resolution Period
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General purpose timer unit
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11
General purpose timer unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module.
11.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 34 lists the timer input frequencies, resolution and periods for each prescaler option at 40 MHz CPU clock. In Incremental Interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3.
Table 34.
GPT1 timer input frequencies, resolutions and periods at 40 MHz
Timer input selection T2I / T3I / T4I
fCPU = 40 MHz 000b Prescaler factor Input frequency Resolution Period maximum 8 5 MHz 200ns 13.1ms 001b 16 2.5 MHz 400ns 26.2ms 010b 32 1.25 MHz 0.8s 52.4ms 011b 64 625 kHz 1.6s 104.8 ms 100b 128 101b 256 110b 512 111b 1024 39.1 kHz 25.6s 1.678s
312.5 kHz 156.25 kHz 78.125 kHz 3.2s 209.7ms 6.4s 419.4ms 12.8s 838.9ms
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ST10F272M Figure 10. Block diagram of GPT1
T2EUD CPU Clock T2IN
2n n=3...10 U/D
General purpose timer unit
GPT1 Timer T2 T2 Mode Control
Reload Capture
Interrupt Request
CPU Clock T3IN T3EUD
2n n=3...10
T3 Mode Control
T3OUT GPT1 Timer T3
U/D Capture
T3OTL
T4IN CPU Clock
2n n=3...10
T4 Mode Control
Reload
Interrupt Request GPT1 Timer T4
U/D
Interrupt Request
T4EUD
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11.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface mode. Table 35 lists the timer input frequencies, resolution and periods for each prescaler option at 40 MHz CPU clock.
Table 35.
GPT2 timer input frequencies, resolutions and periods at 40 MHz
Timer Input Selection T5I / T6I
fCPU = 40 MHz 000b Prescaler factor Input frequency Resolution Period maximum 4 10 MHz 100ns 6.55ms 001b 8 5 MHz 200ns 13.1ms 010b 16 2.5 MHz 400ns 26.2ms 011b 32 1.25 MHz 0.8s 52.4ms 100b 64 625 kHz 1.6s 104.8ms 101b 128 312.5 kHz 3.2s 209.7ms 110b 256 156.25 kHz 6.4s 419.4ms 111b 512 78.125 kHz 12.8s 838.9ms
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ST10F272M Figure 11. Block diagram of GPT2
T5EUD CPU Clock T5IN
U/D 2n n=2...9
General purpose timer unit
T5 Mode Control
GPT2 Timer T5
Clear Capture
Interrupt Request
CAPIN GPT2 CAPREL
Reload
Interrupt Request
Interrupt Request
Toggle FF
T6IN CPU Clock T6EUD
2n n=2...9
T6 Mode Control
GPT2 Timer T6
U/D
T60TL
T6OUT to CAPCOM Timers
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PWM modules
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12
PWM modules
Two pulse width modulation modules are available on ST10F272M: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or center-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. Table 36 shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM modules can generate interrupt requests. Figure 12. Block diagram of PWM module
PPx Period Register * Match
Comparator
Clock 1 Clock 2
Input Control
Run
* PTx 16-bit Up/Down Counter Match
Up/Down/ Clear Control
Comparator
Output Control Enable
POUTx
Shadow Register
Write Control
* User readable / writeable register
PWx Pulse Width Register *
Table 36.
Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64
PWM unit frequencies and resolutions at 40 MHz CPU clock
Resolution 25ns 1.6s Resolution 25ns 1.6s 8-bit 156.25 kHz 2.44 kHz 8-bit 78.12 kHz 1.22 kHz 10-bit 39.1 kHz 610Hz 10-bit 19.53 kHz 305.17Hz 12-bit 9.77 kHz 152.6Hz 12-bit 4.88 kHz 76.29Hz 14-bit 2.44Hz 38.15Hz 14-bit 1.22 kHz 19.07Hz 16-bit 610Hz 9.54Hz 16-bit 305.2Hz 4.77Hz
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ST10F272M
Parallel ports
13
13.1
Parallel ports
Introduction
The ST10F272M MCU provides up to 111 I/O lines with programmable features. These capabilities permit this MCU to be adapted to a wide range of applications. ST10F272M has nine groups of I/O lines gathered as follows:

Port 0 is a two time 8-bit port named P0L (low as less significant byte) and P0H (high as most significant byte) Port 1 is a two time 8-bit port named P1L and P1H Port 2 is a 16-bit port Port 3 is a 15-bit port (P3.14 line is not implemented) Port 4 is an 8-bit port Port 5 is a 16-bit port input only Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers. The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits. A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a pin configured as an output (DPx.y = `1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. I/O lines support an alternate function which is detailed in the following description of each port.
13.2
13.2.1
I/O's special features
Open drain mode
Some of the I/O ports of ST10F272M support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to provide an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx.
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13.2.2
Input threshold control
The standard inputs of the ST10F272M determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. The Port Input Control registers PICON and XPICON are used to select these thresholds for each byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each. All options for individual direction and output mode control are available for each pin, independent of the selected input threshold.
13.3
Alternate port functions
Each port line has one associated programmable alternate input or output function.
PORT0 and PORT1 may be used as address and data lines when accessing external memory. Additionally, PORT1 provides: - - Input capture lines 8 additional analog input channels to the A/D converter
Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1. Port 2 is also used for fast external interrupt inputs and for timer 7 input. Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 4 outputs the additional segment address bit A23...A16 in systems where more than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I2C lines are provided. Port 5 is used as analog input channels of the A/D converter or as timer control signals. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals and the SSC1 lines.

If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y = `1'), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a `1', because its output is ANDed with the alternate output data (except for PWM output signals). If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y = `0') if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, the direction for this pin can also be set to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin.
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ST10F272M
Parallel ports This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches, check how the alternate data output is combined with the respective port latch output. There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. All port lines that are not used for these alternate functions may be used as general purpose I/O lines.
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A/D converter
ST10F272M
14
A/D converter
A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. The ST10F272M has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in an XBus register. Refer to the User Manual for a detailed description. A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 channels. Refer to Section 24: Electrical characteristics for details. The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5LSB (2mV) impacting the global TUE (TUE also depends on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is approximately 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave must be reduced to 800 Hz. If static signal is applied during sampling phase, series resistance must not be greater than 20k (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10nF to minimize the accuracy impact. Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F272M supports different conversion modes:
Single channel single conversion: The analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. Single channel continuous conversion: The analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. Auto scan single conversion: The analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer. Auto scan continuous conversion: The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
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ST10F272M
A/D converter register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer.
Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold. Channel injection mode: When using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630 CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: The bit ADBSY has to be polled to verify that the calibration is over, and the module is able to start a conversion.
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Serial channels
ST10F272M
15
Serial channels
Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and SSC1). Dedicated baudrate generators set up all standard baudrates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and SSC1 (XBUS mapped).
15.1
Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F272M and other microcontrollers, microprocessors or external peripherals.
15.2
ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 1.25 Mbaud (at 40 MHz of fCPU) is supported in this mode.
Table 37.
ASC asynchronous baudrates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baudrate (baud) 833 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 102 Deviation error 0.0% / 0.0% +6.3% / -7.0% +6.3% / -0.8% +3.3% / -1.4% +0.9% / -1.4% +0.9% / -0.2% +0.4% / -0.2% +0.1% / -0.2% +0.1% / -0.1% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 0006 / 0007 000D / 000E 0014 / 0015 002A / 002B 0055 / 0056 00AC / 00AD 015A / 015B 02B5 / 02B6 056B / 056C 0AD8 / 0AD9 1FE8 / 1FE9
Baudrate (baud) 1 250 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 300 153
Deviation error 0.0% / 0.0% +1.5% / -7.0% +1.5% / -3.0% +1.7% / -1.4% +0.2% / -1.4% +0.2% / -0.6% +0.2% / -0.2% +0.2% / 0.0% 0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 000A / 000B 0015 / 0016 001F / 0020 0040 / 0041 0081 / 0082 0103 / 0104 0207 / 0208 0410 / 0411 0822 / 0823 1045 / 1046 1FE8 / 1FE9
Note:
The deviation errors given in the Table 37 are rounded off. To avoid deviation errors use a baudrate crystal (providing a multiple of the ASC0 sampling frequency).
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Serial channels
15.3
ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F272M. Half-duplex communication up to 5 Mbaud (at 40 MHz of fCPU) is possible in this mode.
Table 38.
ASC synchronous baudrates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baudrate (baud) 3 333 333 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 407 Deviation error 0.0% / 0.0% +2.6% / -0.8% +0.9% / -0.8% +0.9% / -0.2% +0.4% / -0.2% +0.1% / -0.2% +0.1% / -0.1% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0% Reload value (hex) 0000 / 0000 001C / 001D 003A / 003B 0055 / 0056 00AC / 00AD 015A / 015B 02B5 / 02B6 056B / 056C 0AD8 / 0AD9 15B2 / 15B3 1FFD / 1FFE
Baudrate (baud) 5 000 000 112 000 56 000 38 400 19 200 9 600 4 800 2 400 1 200 900 612
Deviation error 0.0% / 0.0% +1.5% / -0.8% +0.3% / -0.8% +0.2% / -0.6% +0.2% / -0.2% +0.2% / 0.0% +0.1% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0% 0.0% / 0.0%
Reload value (hex) 0000 / 0000 002B / 002C 0058 / 0059 0081 / 0082 0103 / 0104 0207 / 0208 0410 / 0411 0822 / 0823 1045 / 1046 15B2 / 15B3 1FE8 / 1FE9
Note:
The deviation errors given in the Table 38 are rounded off. To avoid deviation errors use a baudrate crystal (providing a multiple of the ASC0 sampling frequency).
15.4
High speed synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible highspeed serial communication between the ST10F272M and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baudrate generator provides the SSCx with a separate serial clock signal. The serial channel SSCx has its own dedicated 16-bit baudrate generator with 16-bit reload capability, allowing baudrate generation independent from the timers. Table 39 lists some possible baudrates against the required reload values and the resulting bit times for the 40 MHz CPU clock. The maximum is limited to 8 Mbaud.
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Serial channels Table 39. Synchronous baudrate and reload values (fCPU = 40 MHz)
Baudrate Reserved Can be used only with fCPU = 32 MHz (or lower) 6.6 Mbaud 5 Mbaud 2.5 Mbaud 1 Mbaud 100 Kbaud 10 Kbaud 1 Kbaud 306 baud Bit time 150ns 200ns 400ns 1s 10s 100s 1ms 3.26ms
ST10F272M
Reload value 0000h 0001h 0002h 0003h 0007h 0013h 00C7h 07CFh 4E1Fh FF4Eh
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ST10F272M
I2C interface
16
I2C interface
The integrated I2C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s (both Standard and Fast I2C bus modes are supported). The module can generate three different types of interrupt:

requests related to bus events, such as start or stop events, or arbitration lost requests related to data transmission requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as Error, Transmit, and Receive interrupt lines. When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration. When the I2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. The speed of the I2C interface can be selected between Standard mode (0 to 100 kHz) and Fast I2C mode (100 to 400 kHz).
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CAN modules
ST10F272M
17
CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Because of duplication of the CAN controllers, the following adjustments are to be considered:
Same internal register addresses of both CAN controllers, but with base addresses differing in address bit A8; separate chip select for each CAN module. Refer to Chapter 4: Memory organization on page 21. The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin. The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin. Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X-Peripherals sharing the four vectors. The CAN modules must be selected with corresponding CANxEN bit of XPERCON register before the bit XPEN of SYSCON register is set. The reset default configuration is: CAN1 enabled, CAN2 disabled.

Note:
If one or both CAN modules is used, Port 4 cannot be programmed to output all eight segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).
17.1
Configuration support
It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with P4.7 (transmit lines configured to be configured as Open-Drain). The user may also internally map both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 can be used either as general purpose I/O lines, or used for I2C interface. This is possible by setting bit CANPAR of the XMISC register. To access this register it is necessary to set bit XMISCEN of the XPERCON register and bit XPEN of the SYSCON register.
17.2
CAN bus configurations
Depending on the application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F272M can support both configurations.
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ST10F272M
CAN modules
17.2.1
Single CAN bus
The single CAN bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 13. Figure 13. Connection to single CAN bus via separate CAN transceivers
XMISC.CANPAR = 0 CAN1 RX TX CAN2 RX TX
P4.5
P4.6 P4.4
P4.7
CAN Transceiver CAN_H CAN_L
CAN Transceiver
CAN bus
The ST10F272M also supports single CAN bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 14. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. Figure 14. Connection to single CAN bus via common CAN transceivers
XMISC.CANPAR = 0 CAN1 RX +5V P4.5 2.7kW P4.6 P4.4 OD P4.7 OD TX CAN2 RX TX
CAN Transceiver CAN_H CAN_L CAN bus OD = Open Drain Output
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CAN modules
ST10F272M
17.2.2
Multiple CAN bus
The ST10F272M provides two CAN interfaces to support such kind of bus configuration as shown in Figure 15. Figure 15. Connection to two different CAN buses (for example, gateway application)
XMISC.CANPAR = 0 CAN1 RX TX CAN2 RX TX
P4.5
P4.6 P4.4
P4.7
CAN Transceiver CAN_H CAN_L CAN bus 1
CAN Transceiver CAN_H CAN_L CAN bus 2
17.2.3
Parallel mode
In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16. Figure 16. Connection to one CAN bus with internal parallel mode enabled
XMISC.CANPAR = 1 (Both CAN enabled)
CAN1 RX TX
CAN2 RX TX
P4.5
P4.6
P4.4(1)
P4.7(1)
CAN Transceiver CAN_H CAN_L CAN bus
1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O while they cannot be used as external bus address lines.
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ST10F272M
Real time clock
18
Real time clock
The Real Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can continue running even in Idle or Power-down modes (if so enabled). Registers access is implemented onto the XBUS. This module is designed with the following characteristics:

generation of the current time and date for the system cyclic time based interrupt, on Port2 external interrupts every "RTC basic clock tick" and after n 'RTC basic clock ticks' (n is programmable) if enabled 58-bit timer for long term measurement capability to exit the ST10 chip from Power-down mode (if PWDCFG of SYSCON set) after a programmed delay
The real time clock is based on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example, a 1 second period). This basic reference clock is provided by the 20-bit DIVIDER. This 20-bit counter is driven by an input clock derived from the on-chip CPU clock, predivided by a 1/64 fixed counter. This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit PRESCALER register. The value of the 20-bit RTCP register determines the period of the basic reference clock. A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter that may be initialized with the current system time. This counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of the counter matches the alarm register. The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via the EXISEL register of port 2 and wake up the ST10 chip when running powerdown mode. Using the RTCOFF bit of the RTCCON register, the user may switch off the clock oscillator when entering the power-down mode. The last function implemented in the RTC is to switch off the main on-chip oscillator and the 32 kHz on chip oscillator if the ST10 enters the Power-down mode, so that the chip can be fully switched off (if RTC is disabled). At power-on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 / XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference clock: when Power-down mode is entered, the RTC can either be stopped or left running, and in both the cases the main oscillator is turned off, reducing the power consumption of the device to the minimum required to keep on running the RTC counter and relative reference oscillator. This is also valid if Stand-by mode is entered (switching off the main supply VDD), since both the RTC and the low power oscillator (32 kHz) are biased by the VSTBY. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in Power-down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled).
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Watchdog timer
ST10F272M
19
Watchdog timer
The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. Each of the different reset sources is indicated in the WDTCON register:

Watchdog Timer Reset in case of an overflow Software Reset in case of execution of the SRST instruction Short, Long and Power-On Reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high byte of the watchdog timer register can be set to a prespecified reload value (stored in WDTREL). Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced Table 40 shows the watchdog time range for 40 MHz CPU clock. Table 40. WDTREL reload value (fCPU = 40 MHz)
Prescaler for fCPU = 40 MHz Reload value in WDTREL 2 (WDTIN = `0') FFh 00h 12.8s 3.277ms 128 (WDTIN = `1') 819.2s 209.7ms
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ST10F272M
System reset
20
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 41. Table 41. Reset event definition
Flag PONR RPD status Low Low LHWR Synchronous Long Hardware reset Synchronous Short Hardware SHWR reset Watchdog Timer reset Software reset WDTR SWR High High
(3) (3)
Reset source Power-on reset Asynchronous Hardware reset
Conditions Power-on tRSTIN >(1) tRSTIN > (1032 + 12) TCL + max(4 TCL, 500ns)(2) tRSTIN > max(4 TCL, 500ns)(2) tRSTIN < (1032 + 12) TCL + max(4 TCL, 500ns)(2) WDT overflow SRST instruction execution
1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0. 2. See next Section 20.1 for more details on minimum reset pulse duration. 3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to Sections 20.4, 20.5 and 20.6).
The figures in the upcoming sections 20.2, 20.3, 20.5 and 20.6 use the following terminology:

transparent
= level of the pin affects the internal reset logic
not transparent = level of the pin does not affect internal logic
20.1
Input filter
On the RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all spikes shorter than 50ns. On the other hand, a valid pulse longer than 500ns is required for the ST10 to recognize a reset command. In between 50ns and 500ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations. For this reason all minimum durations mentioned in this chapter for the different kinds of reset events must be carefully evaluated, taking into account the above requirements. In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input reset pulse duration, the operating frequency is a key factor. Examples:

For a CPU clock of 40 MHz, 4 TCL is 50ns, so it would be filtered. In this case the minimum becomes the one imposed by the filter (that is 500ns). For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula is coherent with the limit imposed by the filter.
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System reset
ST10F272M
20.2
Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F272M is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins.
Note:
If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended.
Power-on reset
The asynchronous reset must be used during the power-on of the device. Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize (refer to Section 24: Electrical characteristics), with an already stable VDD. The logic of the ST10F272M does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled. At power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. In particular, the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V for the core logic: This time is computed from when the external reference (VDD) becomes stable (inside specification range, that is, at least 4.5V). This is a constraint for the application hardware (external voltage regulator): The RSTIN pin assertion has to be extended to guarantee the voltage regulator stabilization. A second constraint is imposed by the embedded Flash. When booting from internal memory, starting from RSTIN releasing, it needs a maximum of 1ms for its initialization: before that, the internal reset (RST signal) is not released, so the CPU does not start code execution in internal memory. Note: This is not true if external memory is used (pin EA held low during reset phase). In this case, once the RSTIN pin is released, and after a few CPU clock cycles (Filter delay plus 3...8 TCL), the internal reset signal RST is released as well, so the code execution can start immediately after. Obviously, an eventual access to the data in internal Flash is forbidden before its initialization phase is completed: An eventual access during starting phase will return FFFFh (just at the beginning), while later 009Bh (an illegal opcode trap can be generated). At power-on, the RSTIN pin must be tied low for a minimum time that also includes the startup time of the main oscillator (tSTUP = 1ms for resonator, 10ms for crystal) and PLL synchronization time (tPSUP = 200s): This means if the internal Flash is used, the RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start-up phase (Flash initialization only needs stable V18, but does not need stable system clock since an internal dedicated oscillator is used).
Warning:
It is recommended to provide the external hardware with a current limitation circuitry. This is necessary to avoid permanent damage of the device during the power-on transient, when the capacitance on V18 pin is charged. For
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ST10F272M
System reset the on-chip voltage regulator functionality 10nF is sufficient: In any case, a maximum of 100nF on V18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). External current limitation is nevertheless also recommended to avoid risks of damage in case of a temporary short between V18 and ground: The internal 1.8V drivers are sized to drive currents of several tens of Amps, so the current must be limited by the external hardware. The limit of current is imposed by power dissipation considerations (refer to Section 24: Electrical characteristics).
In the next Figures 17 and 18 Asynchronous Power-on timing diagrams are shown, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded Flash module when selected. Caution: Never power the device without keeping the RSTIN pin grounded: The device could enter into unpredictable states, risking also permanent damage.
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System reset Figure 17. Asynchronous power-on RESET (EA = 1)
ST10F272M
1.2 ms (for resonator oscillation + PLL stabilization) 10.2 ms (for crystal oscillation + PLL stabilization) 1ms (for on-chip VREG stabilization)
VDD
2 TCL
V18 XTAL1 RPD ...
RSTIN RSTF (After Filter) P0[15:13]
50ns 500ns 3..4 TCL transparent not t. not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) FLARST
1ms
RST Latching point of Port0 for system start-up configuration
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ST10F272M Figure 18. Asynchronous power-on RESET (EA = 0)
System reset
1.2ms (for resonator oscillation + PLL stabilization) 10.2ms (for crystal oscillation + PLL stabilization) 1ms (for on-chip VREG stabilization)
VDD
3..8 TCL(1)
V18 XTAL1 RPD ...
RSTIN
50ns 500ns 3..4 TCL
RSTF (After Filter) P0[15:13] transparent
not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent
not t. 8 TCL
ALE
RST Latching point of Port0 for system start-up configuration
1. 3 to 8 TCL depending on clock source selection
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 30, 31 and 32. It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
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System reset Figure 19. Asynchronous hardware RESET (EA = 1)
ST10F272M
(1)
2 TCL
RPD 50ns 500ns RSTIN 50ns 500ns 3..4 TCL not transparent transparent
RSTF (After Filter) P0[15:13]
not t.
not t.
P0[12:2]
not transparent
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (internal) FLARST
1ms
RST Latching point of Port0 for system start-up configuration
1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than 500ns to take into account of Input Filter on RSTIN pin.
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ST10F272M Figure 20. Asynchronous hardware RESET (EA = 0)
System reset
(1)
3..8 TCL(2)
RPD 50ns 500ns RSTIN 50ns 500ns 3..4 TCL not transparent transparent
RSTF (After Filter) P0[15:13]
not t.
P0[12:2]
not transparent
transparent
not t.
P0[1:0]
not transparent
not t. 8 TCL
ALE
RST Latching point of Port0 for system start-up configuration
1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than 500ns to take into account of Input Filter on RSTIN pin. 2. 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: As already mentioned, if internal Flash is used, the restarting occurs after the embedded Flash initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. The timings of asynchronous Hardware Reset sequence are summarized in Figure 19 and Figure 20.
20.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the device, the RSTIN pin must be held low, at least, during 4 TCL (two periods of CPU clock): refer also to Section 20.1 for details on minimum reset pulse duration. The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
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System reset
ST10F272M
register was previously set by software. Note that this bit is always cleared on power-on or after a reset sequence.
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12TCL), the internal reset sequence starts. It is 1024 TCL cycles long: at the end of it, and after other 8TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short Reset is flagged (refer to Chapter 19 for details on reset flags); if it is recognized still low, the Long reset is flagged as well. The major difference between Long and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is possible to change the clock options.
Warning:
In case of a short pulse on RSTIN pin, and when Bidirectional reset is enabled, the RSTIN pin is held low by the internal circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is released, but due to the presence of the input analog filter the internal input reset signal (RSTF in the drawings) is released later (from 50 to 500ns). This delay is in parallel with the additional 8 TCL, at the end of which the internal input reset line (RSTF) is sampled, to decide if the reset event is Short or Long. In particular:

If 8 TCL > 500ns (fCPU < 8 MHz), the reset event is always recognized as Short If 8 TCL < 500ns (fCPU > 8 MHz), the reset event could be recognized either as Short or Long, depending on the real filter delay (between 50 and 500ns) and the CPU frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the P0(15:13) pins becomes transparent, so the system clock can be reconfigured. The port returns not transparent 3-4TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL) and released exactly at that time. Note: When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would generate a Flash reset but not a system reset. In this condition, the Flash answers always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
Exit from synchronous reset state
The reset sequence is extended until the RSTIN level becomes high. Moreover, it is internally prolonged by the Flash initialization when EA = 1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F272M starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figures 21 and 22 where a Short Reset event is shown, with particular emphasis on the fact that it can degenerate into Long Reset: the two figures show the
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ST10F272M
System reset behavior when booting from internal or external memory respectively. Figures 23 and 24 report the timing of a typical synchronous Long Reset, again when booting from internal or external memory.
Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (approximately 2.5V), the reset event becomes immediately asynchronous. In case of hardware reset (short or long) the situation goes immediately to the one illustrated in Figure 19. There is no effect if RPD comes again above the input threshold: the asynchronous reset is completed coherently. To correctly complete a synchronous reset, the value of the capacitance must be big enough to maintain a sufficiently high voltage on the RPD pin for the duration of the internal reset sequence. For a Software or Watchdog reset events, an active synchronous reset is completed regardless of the RPD status. It is important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter).
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System reset Figure 21. Synchronous short / long hardware RESET (EA = 1)
4 TCL(4) 12 TCL RSTIN 50ns 500ns RSTF (After Filter) P0[15:13] not transparent
(1)
ST10F272M
< 1032 TCL
(3)
50ns 500ns
50ns 500ns
2 TCL
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1ms FLARST 1024 TCL RST At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset RSTOUT 8 TCL
RPD
(2)
200A Discharge
VRPD > 2.5V Asynchronous Reset not entered
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1)
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ST10F272M Figure 22. Synchronous short / long hardware RESET (EA = 0)
4 TCL(5) 12 TCL
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent
(1)
System reset
< 1032 TCL
(4)
50 ns 500 ns
50 ns 500 ns
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent 3..8 TCL
(3)
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset RSTOUT 8 TCL
RPD
(2)
200A Discharge
VRPD > 2.5V Asynchronous Reset not entered
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. 3 to 8 TCL depending on clock source selection. 4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1).
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System reset Figure 23. Synchronous long hardware RESET (EA = 1)
4 TCL(2) 12 TCL RSTIN 50ns 500ns RSTF (After Filter) P0[15:13] not transparent 50ns 500ns 50ns 500ns 1024+8 TCL
ST10F272M
2 TCL
3..4 TCL transparent not t.
P0[12:2]
not t.
transparent
not t.
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1ms FLARST 1024+8 TCL RST At this time RSTF is sampled LOW so it is definitely LONG reset RSTOUT
RPD
(1)
200A Discharge
VRPD > 2.5V Asynchronous Reset not entered
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the threshold,the reset is defnitively taken as asynchronous. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by theinternal filter (refer to Section 21.1).
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ST10F272M Figure 24. Synchronous long hardware RESET (EA = 0)
System reset
4 TCL(2) 12 TCL RSTIN 50ns 500ns RSTF (After Filter) P0[15:13]
1024+8 TCL
50ns 500ns
50ns 500ns
3..4 TCL not transparent transparent not t.
P0[12:2]
transparent
not t.
P0[1:0]
not transparent 3..8 TCL(3)
not t. 8 TCL
ALE 1024+8 TCL RST At this time RSTF is sampled LOW so it is LONG reset RSTOUT
RPD
(1)
200A Discharge
VRPD > 2.5V Asynchronous Reset not entered
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 2. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by theinternal filter (refer to Section 21.1). 3. 3 to 8 TCL depending on clock source selection.
20.4
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, for example, to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behavior is the same as for a synchronous short reset, except that only bits P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits P0.7...P0.2 are cleared (that is written at `1'). A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected.
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System reset
ST10F272M
Refer to the next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and 29 for bidirectional.
20.5
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared (that is written at `1'). A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and 29 for bidirectional. Figure 25. SW / WDT unidirectional RESET (EA = 1)
RSTIN 2 TCL not transparent
P0[15:13]
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 7 TCL
IBUS-CS (Internal) 1ms FLARST 1024 TCL RST
RSTOUT
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ST10F272M Figure 26. SW / WDT unidirectional RESET (EA = 0)
RSTIN
System reset
P0[15:13]
not transparent
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST
RSTOUT
20.6
Bidirectional reset
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed. The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction. Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed. When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). At the end of the internal reset sequence the pull down is released and:
After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low eight TCL periods after the internal reset sequence completion (refer to Figure 21 and Figure 22), the Short Reset becomes a Long Reset. On the contrary, if RSTF is sampled high the device simply exits reset state. After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF remains still low for at least four TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to Figure 27 and Figure 28), the Software or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state.
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System reset
ST10F272M
The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of SYSCON is cleared). To be activated again it must be enabled during the initialization routine.
WDTCON flags
Similar to what is highlighted in the previous section, when discussing Short reset and the degeneration into Long reset, comparable situations may occur when Bidirectional reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: When RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it remains still active (low) for a while. It means that depending on the internal clock speed, a short reset may be recognized as a long reset: The WDTCON flags are set accordingly. Moreover, when either Software or Watchdog bidirectional reset events occur, when the RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8TCL after the completion of the internal sequence, the level of RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and WDTCON will flag this last event, masking the previous one (Software or Watchdog reset). Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently internal signal RSTF) is sufficiently held low by the external hardware to inject a Long Hardware reset. After this occurrence, the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event, since a different source is flagged inside WDTCON register. This phenomenon does not occur when internal Flash is selected during reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration well beyond the filter delay. The next Figures 27, 28 and 29 summarize the timing for Software and Watchdog Timer Bidirectional reset events: In particular Figure 29 shows the degeneration into Hardware reset.
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ST10F272M Figure 27. SW / WDT bidirectional RESET (EA = 1)
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
System reset
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent 2 TCL
not t. 7 TCL
IBUS-CS (Internal) 1ms FLARST 1024 TCL RST
RSTOUT
Figure 28. SW / WDT bidirectional RESET (EA = 0)
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON
RSTOUT
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System reset
ST10F272M
Figure 29. SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET
RSTIN 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent 50 ns 500 ns
P0[12:8]
transparent
not t.
P0[7:2]
not transparent
P0[1:0]
not transparent
not t. 8 TCL
ALE 1024 TCL RST At this time RSTF is sampled LOW so HW Reset is entered
RSTOUT
20.7
Reset circuitry
Internal reset circuitry is described in Figure 32. The RSTIN pin provides an internal pull-up resistor of 50k to 250k (The minimum reset time must be calculated using the lowest value). It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output internal reset state signal (synchronous reset, watchdog timer reset or software reset). This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin. This is the case of an external memory running codes before EINIT (end of initialization) instruction is executed. RSTOUT pin is pulled high only when EINIT is executed. The RPD pin provides an internal weak pull-down resistor which discharges external capacitor at a typical rate of 200A. If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F272M is to insert a capacitor C1 between RSTIN pin and VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between RPD pin and VDD. The input RSTIN provides an internal pull-up device equalling a resistor of 50k to 250k (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and / or internal PLL and the on-chip voltage regulator to stabilize.
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ST10F272M
System reset To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason, it is recommended to connect the external R0-C0 circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin discharging at a typical rate of 100-200A. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for C0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure. Figure 30. Minimum external reset circuitry
RSTOUT RSTIN External Hardware + C1 a) Hardware Reset
VCC
R0 RPD + C0
b) For Power-up Reset (and Interruptible Power-down mode)
ST10F272M
The minimum reset circuit of Figure 30 is not adequate when the RSTIN pin is driven from the ST10F272M itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence. Figure 31 shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from Power-down mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pull-up for faster recovery and correct biasing of TTL Open Collector drivers.
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System reset Figure 31. System reset circuit
VDD VDD R2
ST10F272M
External Hardware D2 RSTIN VDD D1 o.d. R0 Open Drain Inverter RPD + C0 External Reset Source + C1 R1
ST10F272M
Figure 32. Internal (simplified) reset circuitry
EINIT Instruction Clr Q Set RSTOUT
Reset State Machine Clock VDD
Internal Reset Signal
Trigger Clr
SRST instruction watchdog overflow RSTIN BDRSTEN Reset Sequence (512 CPU Clock Cycles)
VDD Asynchronous Reset
RPD From/to Exit Powerdown Circuit
Weak Pulldown (~200A)
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ST10F272M
System reset
20.8
Reset application examples
The next two timing diagrams (Figure 33 and Figure 34) provide additional examples of bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to Figure 31 for the external circuit scheme). Figure 33. Example of software or watchdog bidirectional reset (EA = 1)
EINIT
00h
not transparent
not transparent
not transparent
Latching point
Latching point
not transparent P0[1:0] not transparent Latching point
3..8 TCL
1Ch
Tfilter RST < 500 ns
< 4 TCL
Latching point
transparent
1 ms (C1 charge)
4 TCL
0Ch
transparent
1024 TCL (12.8 us)
not transparent
VIH
VIL
VIL
WDTCON [5:0]
RSTOUT
P0[15:13]
P0[12:8]
not transparent
RSTIN
RSTF ideal
RST
P0[7:2]
RPD
not transparent
Tfilter RST < 500 ns
04h
transparent
97/176
98/176
1024 TCL (12.8 us) 1 ms (C1 charge) 3..8 TCL EINIT Tfilter RST < 500 ns Tfilter RST < 500 ns 4 TCL
System reset
RSTOUT
VIH
RSTIN
VIL
RSTF ideal
RPD
VIL
RST
WDTCON [5:0]
04h
0Ch
1Ch
< 4 TCL
00h
P0[15:13]
not transparent
transparent Latching point
not transparent
P0[12:8] not transparent
transparent Latching point
not transparent
P0[7:2] not transparent
transparent Latching point not transparent Latching point
Figure 34. Example of software or watchdog bidirectional reset (EA = 0)
not transparent
ST10F272M
P0[1:0]
not transparent
ST10F272M
System reset
20.9
Table 42.
Reset summary
The following table summarizes the different reset events. Reset event
Synch. Asynch. RSTIN Min 1 ms (VREG) 1.2 ms (Reson. + PLL) 10.2 ms (Crystal + PLL) 1ms (VREG) Max WDTCON flags SHWR LHWR WDTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PONR SWR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bidir RPD 0 EA 0
Event
N Asynch.
-
1
1
1
Power-on Reset 0 1 x 0 Hardware Reset (Asynchronous) 0 0 0 1 1 Short Hardware Reset (Synchronous) (1) 1 x x 0 1 0 1 0 1 N Asynch. x Y N Asynch. N Asynch. Y Y Asynch. Asynch.
FORBIDDEN -
1
1
1
500ns 500ns 500ns 500ns max (4 TCL, 500ns) max (4 TCL, 500ns) max (4 TCL, 500ns)
1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns)
0 0 0 0 0 0
1 1 1 1 0 0
1 1 1 1 1 1
N Synch. N Synch.
1
0
Y
Synch.
0
0
1
Activated by internal logic for 1024 TCL max (4 TCL, 500ns) 1 1 Y Synch. 1032 + 12 TCL + max(4 TCL, 500ns)
0
0
1
Activated by internal logic for 1024 TCL 1 1 Long Hardware Reset (Synchronous) 0 1 N Synch. N Synch. 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 1 1 0 0 1 1 1 1
1
0
Y
Synch.
Activated by internal logic only for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) 0 1 1
1
1
Y
Synch.
Activated by internal logic only for 1024 TCL
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System reset Table 42. Reset event (continued)
Synch. Asynch. RSTIN Min Not activated Not activated Not activated Activated by internal logic for 1024 TCL Not activated Not activated Not activated Activated by internal logic for 1024 TCL Max
ST10F272M
WDTCON flags SHWR LHWR WDTR 0 0 0 0 1 1 1 1 X X X X P0L.0 Emu mode PONR SWR 1 1 1 1 1 1 1 1 X X X X P0L.1 Adapt mode
Event
x Software Reset (2) x 0 1 x Watchdog Reset (2) x 0 1
0 0 1 1 0 0 1 1
N Synch. N Synch. Y Y Synch. Synch.
Bidir
RPD
EA
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
N Synch. N Synch. Y Y Synch. Synch.
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details). 2. When Bidirectional is active (and with RPD = 0), it can be followed by a Short Hardware Reset and consequently differently flagged (see Section 20.6 for details).
The start-up configurations and some system features are selected on reset sequences as described in Table 43 and Figure 35. Table 43 describes the system configuration latched on PORT0 in the six different reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON, BUSCON0 registers. Table 43. PORT0 latched configuration for the different reset events
PORT0 P0H.0 WR configuration Clock options Segment address lines Chip selects
Reserved P0L.3 X X X X
Reserved
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0L.7
P0L.6
P0L.5
P0L.4
Sample event Software Reset Watchdog Reset Synchronous Short Hardware Reset Synchronous Long Hardware Reset Asynchronous Hardware Reset Asynchronous Power-On Reset
X X X
X X X
X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X X X
X X X X
X X X X
X X X X
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P0L.2 -
Reserved
Bus type
BSL
X: Pin is sampled -: Pin is not sampled
ST10F272M Figure 35. PORT0 bits latched into the different registers after reset
PORT0
H.7 H.6 CLKCFG H.5 H.4 H.3 H.2 H.1 H.0 WRC L.7 L.6 L.5 BSL L.4 L.3 L.2 Res. L.1 ADP L.0 EMU
System reset
SALSEL
CSSEL
BUSTYP
RP0H
CLKCFG SALSEL CSSEL WRC
Bootstrap Loader
Internal Control Logic
Clock Generator
Port 4 Logic
Port 6 Logic P0L.7
2
EA / VSTBY
P0L.7
SYSCON
ROMEN BYTDIS 10 9 8 7 WRCFG BUS ACT0 ALE CTL0 BTYP
BUSCON0
10
9
7
6
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Power reduction modes
ST10F272M
21
Power reduction modes
Three different power reduction modes with different levels of power reduction have been implemented in the ST10F272M. In Idle mode only CPU is stopped, while peripheral still operate. In Power-down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (VDD) can be turned off while a portion of the internal RAM remains powered via VSTBY dedicated power pin. Idle and Power-down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. Stand-by mode is entered simply removing VDD, holding the MCU under reset state.
Note:
All external bus actions are completed before Idle or Power-down mode is entered. However, Idle or Power-down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access.
21.1
Idle mode
Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run. Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt (RETI) instruction, then the CPU resumes the normal program.
21.2
Power-down mode
Power-down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. The only exception could be the Real Time Clock if opportunely programmed and one of the two oscillator circuits as a consequence (either the main or the 32 kHz on-chip oscillator). When Real Time Clock module is used, when the device is in Power-down mode a reference clock is needed. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction:
A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4) and running. In this case the main oscillator is stopped when Power-down mode is entered, while the Real Time Clock continue counting using 32 kHz clock signal as reference. The presence of a running low-power oscillator is detected after the Poweron: this clock is immediately assumed (if present, or as soon as it is detected) as reference for the Real Time Clock counter and it will be maintained forever (unless specifically disabled via software). Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main oscillator is not stopped when Power-down is entered, and the Real Time Clock continue counting using the main oscillator clock signal as reference.
There are two different operating Power-down modes: protected mode and interruptible mode.
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ST10F272M
Power reduction modes Before entering Power-down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set.
Note:
Leaving the main voltage regulator active during Power-down may lead to unexpected behavior (example: CPU wake-up) and power consumption higher than what is specified.
21.2.1
Protected power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected Power-down mode is only activated if the NMI pin is pulled low when executing PWRDN instruction (this means that the PWRD instruction belongs to the NMI software routine). This mode is only deactivated with an external hardware reset on RSTIN pin.
21.2.2
Interruptible power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set. The Interruptible Power-down mode is only activated if all the enabled Fast External Interrupt pins are in their inactive level. This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt request applied to one of the Fast External Interrupt pins, or with an interrupt generated by the Real Time Clock, or with an interrupt generated by the activity on CAN's and I2C module interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low according the recommendations described in Chapter 20: System reset on page 77. An external RC circuit must be connected to RPD pin, as shown in the Figure 36. Figure 36. External RC circuitry on RPD pin
ST10F272M VDD R0
220k minimum
RPD
+
C0
1F Typical
To exit Power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns.
21.3
Stand-by mode
In Stand-by mode, it is possible to turn off the main VDD provided that VSTBY is available through the dedicated pin of the ST10F272M. To enter Stand-by mode it is mandatory to held the device under reset: once the device is under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital interface is frozen in order to avoid any kind of data corruption. A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16 Kbytes for ST10F272M), the RTC counters and 32 kHz onchip oscillator amplifier.
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Power reduction modes
ST10F272M
In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz oscillator used in conjunction with Real Time Clock module), is granted by the active main VDD. It must be noted that Stand-by mode can generate problems associated with the usage of different power supplies in CMOS systems; particular attention must be paid when the ST10F272M I/O lines are interfaced with other external CMOS integrated circuits: if VDD of ST10F272M becomes (for example, in Stand-by mode) lower than the output level forced by the I/O lines of these external integrated circuits, the ST10F272M could be directly powered through the inherent diode existing on ST10F272M output driver circuitry. The same is valid for ST10F272M interfaced to active/inactive communication buses during Stand-by mode: current injection can be generated through the inherent diode. Furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the ST10F272M device). The device Stand-by mode current (ISTBY) may vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this phenomenon.
21.3.1
Entering stand-by mode
As already stated, to enter Stand-by mode the XRAM2EN bit in the XPERCON register must be cleared: This allows the RAM interface to be frozen immediately, avoiding any data corruption. As a consequence of a RESET event, the RAM power supply is switched to the internal low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator). The RAM interface remains frozen until the bit XRAM2EN is set again by software initialization routine (at next exit from main VDD power-on reset sequence). Since V18 is falling down (as a consequence of VDD turning off), it can happen that the XRAM2EN bit is no longer able to guarantee its content (logic "0"), being the XPERCON Register powered by internal V18. This does not generate any problem, because the Standby mode switching dedicated circuit continues to confirm the RAM interface freezing, irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when internal V18 comes back over internal stand-by reference V18SB. If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45V with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V18 voltage versus internal V18SB during normal code execution, no spurious Stand-by mode switching can occur (the RAM is not frozen and can still be accessed). The ST10F272M Core module, generating the RAM control signals, is powered by internal V18 supply; during turning off transient these control signals follow the V18, while RAM is switched to V18SB internal reference. It could happen that a high level of RAM write strobe from ST10F272M Core (active low signal) is low enough to be recognized as a logic "0" by the RAM interface (due to V18 lower than V18SB): The bus status could contain a valid address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism.
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ST10F272M
Power reduction modes
Warning:
During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply.
21.3.2
Exiting stand-by mode
After the system has entered the Stand-by mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V18SB internal reference (derived from VSTBY pin external voltage). It is recommended to held the device under RESET (RSTIN pin forced low) until external VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V18 becomes higher than about 1.0V, there is no guaranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch. The external hardware is responsible for driving the RSTIN pin low until the VDD is stable, even though the internal LVD is active. Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V18. At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM.
21.3.3
Real time clock and stand-by mode
When Stand-by mode is entered (turning off the main supply VDD), the Real Time Clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: Being the main oscillator powered by VDD, once this is switched off, the oscillator is stopped.
21.3.4
Power reduction modes summary
The different Power reduction modes are summarized in the following Table 44.
Table 44.
Power reduction modes summary
STBY XRAM 32 kHz OSC Peripherals Main OSC XRAM biased biased 105/176 VSTBY CPU RTC off on VDD on
Mode
on on
off off
on on
run run
off on
biased biased
Idle on
Power reduction modes Table 44. Power reduction modes summary (continued)
STBY XRAM 32 kHz OSC Peripherals Main OSC
ST10F272M
Mode
on Power-down on on off Stand-by off
on on on on on
off off off off off
off off off off off
off on on off on
off on off off off
off off on off on
biased biased biased biased biased
biased biased biased off off
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XRAM
VSTBY
CPU
RTC
VDD
ST10F272M
Programmable output clock divider
22
Programmable output clock divider
A specific register mapped on the XBUS can be used to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed.
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Register set
ST10F272M
23
Register set
This section summarizes all registers implemented in the ST10F272M, ordered by name.
23.1
Special function registers
The following table lists all SFRs which are implemented in the ST10F272M in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address".
Table 45.
Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC
List of special function registers
Physical address b b FF98h FFA0h FEA0h F0A0h FE18h FE1Ah FE1Ch FE1Eh b FF9Ah FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FE80h b FF78h FE82h b FF7Ah FE84h b FF7Ch FE86h b FF7Eh E 8-bit address CCh D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25h 40h BCh 41h BDh 42h BEh 43h BFh Description A/D converter end of conversion interrupt control register A/D converter control register A/D converter result register A/D converter 2 result register Address select register 1 Address select register 2 Address select register 3 Address select register 4 A/D converter overrun error interrupt control register Bus configuration register 0 Bus configuration register 1 Bus configuration register 2 Bus configuration register 3 Bus configuration register 4 GPT2 capture/reload register CAPCOM register 0 CAPCOM register 0 interrupt control register CAPCOM register 1 CAPCOM register 1 interrupt control register CAPCOM register 2 CAPCOM register 2 interrupt control register CAPCOM register 3 CAPCOM register 3 interrupt control register Reset value - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0xx0h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h
BUSCON0 b BUSCON1 b BUSCON2 b BUSCON3 b BUSCON4 b CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC
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ST10F272M Table 45.
Name CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC b b b b b b b b b b b b b b b b b
Register set List of special function registers (continued)
Physical address FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h FE92h FF8Ah FE94h FF8Ch FE96h FF8Eh FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h F160h FE62h F162h FE64h F164h FE66h F166h FE68h F168h E E E E E 8-bit address 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h 49h C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h CAPCOM register 4 CAPCOM register 4 interrupt control register CAPCOM register 5 CAPCOM register 5 interrupt control register CAPCOM register 6 CAPCOM register 6 interrupt control register CAPCOM register 7 CAPCOM register 7 interrupt control register CAPCOM register 8 CAPCOM register 8 interrupt control register CAPCOM register 9 CAPCOM register 9 interrupt control register CAPCOM register 10 CAPCOM register 10 interrupt control register CAPCOM register 11 CAPCOM register 11 interrupt control register CAPCOM register 12 CAPCOM register 12 interrupt control register CAPCOM register 13 CAPCOM register 13 interrupt control register CAPCOM register 14 CAPCOM register 14 interrupt control register CAPCOM register 15 CAPCOM register 15 interrupt control register CAPCOM register 16 CAPCOM register 16 interrupt control register CAPCOM register 17 CAPCOM register 17 interrupt control register CAPCOM register 18 CAPCOM register 18 interrupt control register CAPCOM register 19 CAPCOM register 19 interrupt control register CAPCOM register 20 CAPCOM register 20 interrupt control register Description Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h
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Register set Table 45.
Name CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L b b b b b b b b b b b b b b b b b b b b b
ST10F272M
List of special function registers (continued)
Physical address FE6Ah F16Ah FE6Ch F16Ch FE6Eh F16Eh FE70h F170h FE72h F172h FE74h F174h FE76h F176h FE78h F178h FE7Ah F184h FE7Ch F18Ch FE7Eh F194h FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h FF6Ah FE08h F100h E E E E E E E E E E E E 8-bit address 35h B5h 36h B6h 37h B7h 38h B8h 39h B9h 3Ah BAh 3Bh BBh 3Ch BCh 3Dh C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h 80h Description CAPCOM register 21 CAPCOM register 21 interrupt control register CAPCOM register 22 CAPCOM register 22 interrupt control register CAPCOM register 23 CAPCOM register 23 interrupt control register CAPCOM register 24 CAPCOM register 24 interrupt control register CAPCOM register 25 CAPCOM register 25 interrupt control register CAPCOM register 26 CAPCOM register 26 interrupt control register CAPCOM register 27 CAPCOM register 27 interrupt control register CAPCOM register 28 CAPCOM register 28 interrupt control register CAPCOM register 29 CAPCOM register 29 interrupt control register CAPCOM register 30 CAPCOM register 30 interrupt control register CAPCOM register 31 CAPCOM register 31 interrupt control register CAPCOM Mode Control register 0 CAPCOM Mode Control register 1 CAPCOM Mode Control register 2 CAPCOM mode Control register 3 CAPCOM Mode Control register 4 CAPCOM Mode Control register 5 CAPCOM Mode Control register 6 CAPCOM Mode Control register 7 CPU Context Pointer register GPT2 CAPREL interrupt control register CPU Code Segment Pointer register (read only) P0L direction control register Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h - - 00h 0000h - - 00h
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ST10F272M Table 45.
Name DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EMUCON EXICON EXISEL IDCHIP IDMANUF IDMEM IDPROG IDX0 IDX1 MAH MAL MCW MDC MDH MDL MRW MSW ODP2 ODP3 ODP4 ODP6 b b b b b b b b b b b b b b b b b b b b b
Register set List of special function registers (continued)
Physical address F102h F104h F106h FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h FE0Ah F1C0h F1DAh F07Ch F07Eh F07Ah F078h FF08h FF0Ah FE5Eh FE5Ch FFDCh FF0Eh FE0Ch FE0Eh FFDAh FFDEh F1C2h F1C6h F1CAh F1CEh E E E E E E E E E E E E E 8-bit address 81h 82h 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h 05h E0h EDh 3Eh 3Fh 3Dh 3Ch 84h 85h 2Fh 2Eh EEh 87h 06h 07h EDh EFh E1h E3h E5h E7h Description P0h direction control register P1L direction control register P1h direction control register Port 2 direction control register Port 3 direction control register Port 4 direction control register Port 6 direction control register Port 7 direction control register Port 8 direction control register CPU data page pointer 0 register (10-bit) CPU data page pointer 1 register (10-bit) CPU data page pointer 2 register (10-bit) CPU data page pointer 3 register (10-bit) Emulation control register External interrupt control register External interrupt source selection register Device identifier register (n is the device revision) Manufacturer identifier register On-chip memory identifier register Programming voltage identifier register MAC unit address pointer 0 MAC unit address pointer 1 MAC unit accumulator - high word MAC unit accumulator - low word MAC unit control word CPU multiply divide control register CPU multiply divide register - high word CPU multiply divide register - low word MAC unit repeat word MAC unit status word Port 2 open drain control register Port 3 open drain control register Port 4 open drain control register Port 6 open drain control register Reset value - - 00h - - 00h - - 00h 0000h 0000h - - 00h - - 00h - - 00h - - 00h 0000h 0001h 0002h 0003h - - XXh 0000h 0000h 110nh 0403h 2040h 0040h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0200h 0000h 0000h - - 00h - - 00h
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Register set Table 45.
Name ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 P8 P5DIDIS PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSW PT0 PT1 PT2 PT3 PW0 b b b b b b b b b b b b b b b b b
ST10F272M
List of special function registers (continued)
Physical address F1D2h F1D6h FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FFD4h FFA4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh F1C4h F038h F03Ah F03Ch F03Eh FF10h F030h F032h F034h F036h FE30h E E E E E E E E E E E 8-bit address E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h EAh D2h 60h 61h 62h 63h 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h 1Ah 1Bh 18h Description Port 7 open drain control register Port 8 open drain control register Constant value 1's register (read only) PORT0 low register (lower half of PORT0) PORT0 high register (upper half of PORT0) PORT1 low register (lower half of PORT1) PORT1 high register (upper half of PORT1) Port 2 register Port 3 register Port 4 register (8-bit) Port 5 register (read only) Port 6 register (8-bit) Port 7 register (8-bit) Port 8 register (8-bit) Port 5 digital disable register PEC channel 0 control register PEC channel 1 control register PEC channel 2 control register PEC channel 3 control register PEC channel 4 control register PEC channel 5 control register PEC channel 6 control register PEC channel 7 control register Port input threshold control register PWM module period register 0 PWM module period register 1 PWM module period register 2 PWM module period register 3 CPU program status word PWM module up/down counter 0 PWM module up/down counter 1 PWM module up/down counter 2 PWM module up/down counter 3 PWM module pulse width register 0 Reset value - - 00h - - 00h FFFFh - - 00h - - 00h - - 00h - - 00h 0000h 0000h - - 00h XXXXh - - 00h - - 00h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F272M Table 45.
Name PW1 PW2 PW3 PWMCON0 b PWMCON1 b PWMIC QR0 QR1 QX0 QX1 RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T0 T01CON T0IC T0REL b b b b b b b b b b b b b b
Register set List of special function registers (continued)
Physical address FE32h FE34h FE36h FF30h FF32h F17Eh F004h F006h F000h F002h F108h FEB4h FFB0h FF70h FEB2h FF6Eh F19Ch FEB0h FF6Ch FE12h F0B4h FFB2h FF76h F0B2h FF74h F0B0h FF72h FE14h FE16h FF12h FE50h FF50h FF9Ch FE54h E E E E E E E E E E 8-bit address 19h 1Ah 1Bh 98h 99h BFh 02h 03h 00h 01h 84h 5Ah D8h B8h 59h B7h CEh 58h B6h 09h 5Ah D9h BBh 59h BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah Description PWM module pulse width register 1 PWM module pulse width register 2 PWM module pulse width register 3 PWM module control register 0 PWM module control register 1 PWM module interrupt control register MAC unit offset register r0 MAC unit offset register R1 MAC unit offset register X0 MAC unit offset register X1 System start-up configuration register (read only) Serial channel 0 baudrate generator reload register Serial channel 0 control register Serial channel 0 error interrupt control register Serial channel 0 receive buffer register (read only) Serial channel 0 receive interrupt control register Serial channel 0 transmit buffer interrupt control reg. Serial channel 0 transmit buffer register (write only) Serial channel 0 transmit interrupt control register CPU system stack pointer register SSC baudrate register SSC control register SSC error interrupt control register SSC receive buffer (read only) SSC receive interrupt control register SSC transmit buffer (write only) SSC transmit interrupt control register CPU stack overflow pointer register CPU stack underflow pointer register CPU system configuration register CAPCOM timer 0 register CAPCOM timer 0 and timer 1 control register CAPCOM timer 0 interrupt control register CAPCOM timer 0 reload register Reset value 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h 0000h 0000h - - XXh 0000h 0000h - - 00h - - XXh - - 00h - - 00h 0000h - - 00h FC00h 0000h 0000h - - 00h XXXXh - - 00h 0000h - - 00h FA00h FC00h 0xx0h(1) 0000h 0000h - - 00h 0000h
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Register set Table 45.
Name T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR WDT WDTCON XADRS3 XP0IC XP1IC XP2IC XP3IC b b b b b b b b b b b b b b b b b b b b
ST10F272M
List of special function registers (continued)
Physical address FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h F050h FF20h F17Ah F054h F052h F17Ch F056h FFACh FEAEh FFAEh F01Ch F186h F18Eh F196h F19Eh E E E E E E E E E E E 8-bit address 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h 28h 90h BDh 2Ah 29h BEh 2Bh D6h 57h D7h 0Eh C3h C7h CBh CFh Description CAPCOM timer 1 register CAPCOM timer 1 interrupt control register CAPCOM timer 1 reload register GPT1 timer 2 register GPT1 timer 2 control register GPT1 timer 2 interrupt control register GPT1 timer 3 register GPT1 timer 3 control register GPT1 timer 3 interrupt control register GPT1 timer 4 register GPT1 timer 4 control register GPT1 timer 4 interrupt control register GPT2 timer 5 register GPT2 timer 5 control register GPT2 timer 5 interrupt control register GPT2 timer 6 register GPT2 timer 6 control register GPT2 timer 6 interrupt control register CAPCOM timer 7 register CAPCOM timer 7 and 8 control register CAPCOM timer 7 interrupt control register CAPCOM timer 7 reload register CAPCOM timer 8 register CAPCOM timer 8 interrupt control register CAPCOM timer 8 reload register Trap Flag register Watchdog timer register (read only) Watchdog timer control register XPER address select register 3 See Section 9.1 See Section 9.1 See Section 9.1 See Section 9.1 Reset value 0000h - - 00h 0000h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h - - 00h 0000h 0000h 0000h 00xxh(2) 800Bh - - 00h(3) - - 00h(3) - - 00h(3) - - 00h(3)
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ST10F272M Table 45.
Name XPERCON b ZEROS b
Register set List of special function registers (continued)
Physical address F024h FF1Ch E 8-bit address 12h 8Eh Description XPER configuration register Constant value 0's register (read only) Reset value - - 05h 0000h
1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset value depends on different triggered reset event.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes.
23.2
X-registers
The following table lists all X-Bus registers which are implemented in the ST10F272M ordered by their name. The Flash control registers are listed in a separate section, in spite of they also are physically mapped on X-Bus memory space.
Note:
The X-Registers are not bit-addressable. Table 46.
Name CAN1BRPER CAN1BTR CAN1CR CAN1EC CAN1IF1A1 CAN1IF1A2 CAN1IF1CM CAN1IF1CR CAN1IF1DA1 CAN1IF1DA2 CAN1IF1DB1 CAN1IF1DB2 CAN1IF1M1 CAN1IF1M2 CAN1IF1MC CAN1IF2A1 CAN1IF2A2 CAN1IF2CM CAN1IF2CR CAN1IF2DA1
List of XBus registers
Physical address EF0Ch EF06h EF00h EF04h EF18h EF1Ah EF12h EF10h EF1Eh EF20h EF22h EF24h EF14h EF16h EF1Ch EF48h EF4Ah EF42h EF40h EF4Eh Description CAN1: BRP extension register CAN1: Bit timing register CAN1: CAN control register CAN1: error counter CAN1: IF1 arbitration 1 CAN1: IF1 arbitration 2 CAN1: IF1 command mask CAN1: IF1 command request CAN1: IF1 data A 1 CAN1: IF1 data A 2 CAN1: IF1 data B 1 CAN1: IF1 data B 2 CAN1: IF1 mask 1 CAN1: IF1 mask 2 CAN1: IF1 message control CAN1: IF2 arbitration 1 CAN1: IF2 arbitration 2 CAN1: IF2 command mask CAN1: IF2 command request CAN1: IF2 data A 1 Reset value 0000h 2301h 0001h 0000h 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0001h 0000h
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Register set Table 46.
Name CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF1M1 CAN2IF1M2 CAN2IF1MC CAN2IF2A1 CAN2IF2A2
ST10F272M List of XBus registers (continued)
Physical address EF50h EF52h EF54h EF44h EF46h EF4Ch EFA0h EFA2h EF08h EFB0h EFB2h EF90h EF92h EF02h EF0Ah EF80h EF82h EE0Ch EE06h EE00h EE04h EE18h EE1Ah EE12h EE10h EE1Eh EE20h EE22h EE24h EE14h EE16h EE1Ch EE48h EE4Ah Description CAN1: IF2 data A 2 CAN1: IF2 data B 1 CAN1: IF2 data B 2 CAN1: IF2 Mask 1 CAN1: IF2 mask 2 CAN1: IF2 message control CAN1: interrupt pending 1 CAN1: interrupt pending 2 CAN1: interrupt register CAN1: message valid 1 CAN1: message valid 2 CAN1: new data 1 CAN1: new data 2 CAN1: status register CAN1: test register CAN1: transmission request 1 CAN1: transmission request 2 CAN2: BRP extension register CAN2: bit timing register CAN2: CAN control register CAN2: error counter CAN2: IF1 arbitration 1 CAN2: IF1 arbitration 2 CAN2: IF1 command mask CAN2: IF1 command request CAN2: IF1 data A 1 CAN2: IF1 data A 2 CAN2: IF1 data B 1 CAN2: IF1 data B 2 CAN2: IF1 mask 1 CAN2: IF1 mask 2 CAN2: IF1 message control CAN2: IF2 arbitration 1 CAN2: IF2 arbitration 2 Reset value 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00x0h 0000h 0000h 0000h 2301h 0001h 0000h 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h
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ST10F272M Table 46.
Name CAN2IF2CM CAN2IF2CR CAN2IF2DA1 CAN2IF2DA2 CAN2IF2DB1 CAN2IF2DB2 CAN2IF2M1 CAN2IF2M2 CAN2IF2MC CAN2IP1 CAN2IP2 CAN2IR CAN2MV1 CAN2MV2 CAN2ND1 CAN2ND2 CAN2SR CAN2TR CAN2TR1 CAN2TR2 I2CCCR1 I2CCCR2 I2CCR I2CDR I2COAR1 I2COAR2 I2CSR1 I2CSR2 RTCAH RTCAL RTCCON RTCDH RTCDL RTCH
Register set List of XBus registers (continued)
Physical address EE42h EE40h EE4Eh EE50h EE52h EE54h EE44h EE46h EE4Ch EEA0h EEA2h EE08h EEB0h EEB2h EE90h EE92h EE02h EE0Ah EE80h EE82h EA06h EA0Eh EA00h EA0Ch EA08h EA0Ah EA02h EA04h ED14h ED12h ED00H ED0Ch ED0Ah ED10h Description CAN2: IF2 command mask CAN2: IF2 command request CAN2: IF2 data A 1 CAN2: IF2 data A 2 CAN2: IF2 data B 1 CAN2: IF2 data B 2 CAN2: IF2 mask 1 CAN2: IF2 mask 2 CAN2: IF2 message control CAN2: interrupt pending 1 CAN2: interrupt pending 2 CAN2: interrupt register CAN2: message valid 1 CAN2: message valid 2 CAN2: new data 1 CAN2: new data 2 CAN2: status register CAN2: test register CAN2: transmission request 1 CAN2: Transmission request 2 I2C clock control register 1 I2C clock control register 2 I2C control register I2C data register I2C own address register 1 I2C own address register 2 I2C status register 1 I2C status register 2 RTC alarm register high byte RTC alarm register low byte RTC control register RTC divider counter high byte RTC divider counter low byte RTC programmable counter high byte Reset value 0000h 0001h 0000h 0000h 0000h 0000h FFFFh FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00x0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh XXXXh 000Xh XXXXh XXXXh XXXXh
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Register set Table 46.
Name RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 XPT0 XPT1 XPT2 XPT3 XPW0
ST10F272M List of XBus registers (continued)
Physical address ED0Eh ED08h ED06h EB02h EB76h EB78h EB7Ah EB7Ch EB14h EB10h EB12h EB24h EB20h EB22h EB34h EB30h EB32h EB44h EB40h EB42h EB46h EB36h EB7Eh EB26h EC04h EC20h EC22h EC24h EC26h EC10h EC12h EC14h EC16h EC30h Description RTC programmable counter low byte RTC prescaler register high byte RTC prescaler register low byte CLKOUT divider control register XBUS emulation register 0 (write only) XBUS emulation register 1 (write only) XBUS emulation register 2 (write only) XBUS emulation register 3 (write only) X-Interrupt 0 clear register (write only) X-Interrupt 0 selection register X-Interrupt 0 set register (write only) X-Interrupt 1 clear register (write only) X-Interrupt 1 selection register X-Interrupt 1 set register (write only) X-Interrupt 2 clear register (write only) X-Interrupt 2 selection register X-Interrupt 2 set register (write only) X-Interrupt 3 clear selection register (write only) X-Interrupt 3 selection register X-Interrupt 3 set selection register (write only) XBUS miscellaneous features register Port 1 digital disable register XPERCON copy for emulation (write only) Extended port input threshold control register XPWM module channel polarity register XPWM module period register 0 XPWM module period register 1 XPWM module period register 2 XPWM module period register 3 XPWM module up/down counter 0 XPWM module up/down counter 1 XPWM module up/down counter 2 XPWM module up/down counter 3 XPWM module pulse width register 0 Reset value XXXXh XXXXh XXXXh - - 00h XXXXh XXXXh XXXXh XXXXh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh - - 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F272M Table 46.
Name XPW1 XPW2 XPW3 XPWMCON0 XPWMCON0CLR XPWMCON0SET XPWMCON1 XPWMCON1CLR XPWMCON1SET XPWMPORT XS1BG XS1CON XS1CONCLR XS1CONSET XS1PORT XS1RBUF XS1TBUF XSSCBR XSSCCON XSSCCONCLR XSSCCONSET XSSCPORT XSSCRB XSSCTB
Register set List of XBus registers (continued)
Physical address EC32h EC34h EC36h EC00h EC08h EC06h EC02h EC0Ch EC0Ah EC80h E906h E900h E904h E902h E980h E90Ah E908h E80Ah E800h E804h E802h E880h E808h E806h Description XPWM module pulse width register 1 XPWM module pulse width register 2 XPWM module pulse width register 3 XPWM module control register 0 XPWM module clear control reg. 0 (write only) XPWM module set control register 0 (write only) XPWM module control register 1 XPWM module clear control reg. 0 (write only) XPWM module set control register 0 (write only) XPWM module port control register XASC baudrate generator reload register XASC control register XASC clear control register (write only) XASC set control register (write only) XASC port control register XASC receive buffer register XASC transmit buffer register XSSC baudrate register XSSC control register XSSC clear control register (write only) XSSC set control register (write only) XSSC port control register XSSC receive buffer XSSC transmit buffer Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXXXh 0000h
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Register set
ST10F272M
23.3
Flash registers ordered by name
The following table lists all Flash Control Registers which are implemented in the ST10F272M ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on XBus. Note that these registers are not bitaddressable. Table 47.
Name FARH FARL FCR0H FCR0L FCR1H FCR1L FDR0H FDR0L FDR1H FDR1L FER FNVAPR0 FNVAPR1H FNVAPR1L FNVWPIR XFVTAUR0
List of Flash registers
Physical address 0x0008 0012 0x0008 0010 0x0008 0002 0x0008 0000 0x0008 0006 0x0008 0004 0x0008 000A 0x0008 0008 0x0008 000E 0x0008 000C 0x0008 0014 0x0008 DFB8 0x0008 DFBE 0x0008 DFBC 0x0008 DFB0 0x0000 EB50 Description Flash address register - high Flash address register - low Flash control register 0 - high Flash control register 0 - low Flash control register 1 - high Flash control register 1 - low Flash data register 0 - high Flash data register 0 - low Flash data register 1 - high Flash data register 1 - low Flash error register Flash non-volatile access protection reg.0 Flash non-volatile access protection reg.1 - high Flash non-volatile access protection reg.1 - low Flash non-volatile protection I register XBus Flash volatile temporary access unprotection register 0 Reset value 0000h 0000h 0000h 0000h 0000h 0000h FFFFh FFFFh FFFFh FFFFh 0000h ACFFh FFFFh FFFFh FFFFh 0000h
23.4
Identification registers
The ST10F272M have four Identification registers, mapped in ESFR space. These registers contain:

A manufacturer identifier A chip identifier with its revision An internal Flash and size identifier Programming voltage description
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ST10F272M
Register set
IDMANUF (F07Eh / 3Fh) 15 14 13 12 11 10 MANUF RO 9 8
ESFR 7 6 5 4 0 RO 3 0 RO
Reset value: 0403h 2 0 RO 1 1 RO 0 1 RO
Table 48.
Bit 15:5
IDMANUF register description
Name MANUF Function Manufacturer identifier 020h: STMicroelectronics manufacturer (JTAG worldwide normalization)
IDCHIP (F07Ch / 3Eh) 15 14 13 12 11 10 9 8
ESFR 7 6 5 4 3
Reset value: 110Xh 2 1 0
IDCHIP RO
REVID RO
Table 49.
Bit 15:4 3:0
IDCHIP register description
Name IDCHIP REVID Function Device identifier 110h: ST10F272M identifier (272) Device revision identifier Xh: According to revision number
IDMEM (F07Ah / 3Dh) 15 14 13 12 11 10 9 8
ESFR 7 6 5 4 3
Reset value: 2040h 2 1 0
MEMTYP RO
MEMSIZE RO
Table 50.
Bit
IDMEM register description
Name Internal memory size Function
15:12
MEMSIZE
Internal memory size is 4 x (MEMSIZE) (in Kbyte) 040h for 256 Kbytes (ST10F272M) Internal memory type
11:0
MEMTYP
0h: ROM-Less 1h: (M) ROM memory 2h: (S) Standard Flash memory (ST10F272M) 3h: (H) High performance Flash memory 4h...Fh: Reserved
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Register set
ST10F272M
IDPROG (F078h / 3Ch) 15 14 13 12 11 10 9 8
ESFR 7 6 5 4 3
Reset value: 0040h 2 1 0
PROGVPP RO
PROGVDD RO
Table 51.
Bit 15:8
IDPROG register description
Name Function
PROGVPP Programming VPP voltage (no need of external VPP) - 00h Programming VDD voltage PROGVDD VDD voltage when programming EPROM or Flash devices is calculated using the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F272M (5V).
7:0
Note:
All identification words are read-only registers.
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ST10F272M
Electrical characteristics
24
24.1
Table 52.
Symbol VDD VSTBY VAREF VAGND VIO IOV ITOV TST ESD
Electrical characteristics
Absolute maximum ratings
Absolute maximum ratings
Parameter Voltage on VDD pins with respect to ground (VSS) Voltage on VSTBY pin with respect to ground (VSS) Voltage on VAREF pins with respect to ground (VSS) Voltage on VAGND pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Storage temperature ESD Susceptibility (Human Body Model) Values -0.5 to +6.5 -0.5 to +6.5 -0.3 to VDD VSS -0.5 to VDD + 0.5 10 | 75 | -65 to +150 2000 Unit V V V V V mA mA C V
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings. During Power-on and Power-off transients (including Standby entering/exiting phases), the relationships between voltages applied to the device and the main VDD must always be respected. In particular, power-on and power-off of VAREF must be coherent with VDD transient, in order to avoid undesired current injection through the on-chip protection diodes.
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Electrical characteristics
ST10F272M
24.2
Table 53.
Symbol VDD VSTBY VAREF TA TJ
Recommended operating conditions
Recommended operating conditions
Value Parameter Min Operating supply voltage Operation stand-by supply voltage(1) Operating analog reference voltage(2) Ambient temperature under bias -40 Junction temperature under bias +150 +125 C 4.5 5.5 V Max Unit
1. The value of the VSTBY voltage is specified in the range of 4.5 to 5.5 volts. When VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on VDD power supply (in the range of tenth of A). 2. For details on operating conditions concerning the usage of A/D Converter refer to Section 24.7.
24.3
Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1) Where: TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power, PI/O represents the Power Dissipation on Input and Output Pins; User Determined. Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 (3) Where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.
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ST10F272M Table 54.
Symbol
Electrical characteristics Thermal characteristics
Description Thermal Resistance Junction-Ambient PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch on four-layer FR4 board (2 layers signals / 2 layers power) Value (typical) Unit
JA
30 40 35
C/W
Based on thermal characteristics of the package and with reference to the power consumption figures provided in the next tables and diagrams, the following product classification can be proposed. However, the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata), I/O activity, and so on. Table 55. Package characteristics
Ambient temperature range -40 to +125C LQFP 144 CPU frequency range 1 to 40 MHz
Package PQFP 144
24.4
Parameter interpretation
The parameters listed in the following tables represent the characteristics of the ST10F272M and its demands on the system. Where the ST10F272M logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F272M, the symbol "SR" for System Requirement, is included in the "Symbol" column.
24.5
Table 56.
DC characteristics
VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125C DC characteristics
Limit values Parameter Symbol Min Max 0.8 V - Unit Test condition
Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage RSTIN, EA, NMI, RPD Input low voltage XTAL1 (CMOS only)
VIL
SR
-0.3
VILS VIL1 VIL2
SR SR SR
-0.3 -0.3 -0.3
0.3 VDD 0.3 VDD 0.3 VDD
V V V
- - Direct Drive mode
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Electrical characteristics Table 56. DC characteristics (continued)
Limit values Parameter Input low voltage READY (TTL only) Input high voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1) Input high voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1) Symbol Min VIL3 VIH VIHS SR SR SR SR SR SR CC -0.3 2.0 0.7 VDD 0.7 VDD 0.7 VDD 2.0 400 750 750 0 400 500 Max 0.8 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 700 1400 1400 50 700 1500 0.4 0.05 V V V V V V mV mV mV mV mV mV Unit
ST10F272M
Test condition - - - - Direct Drive mode -
(1)
Input high voltage RSTIN, EA, NMI, RPD VIH1 Input high voltage XTAL1 (CMOS only) Input high voltage READY (TTL only) Input Hysteresis (TTL mode) (except RSTIN, EA, NMI, XTAL1, RPD) Input Hysteresis (CMOS mode) (except RSTIN, EA, NMI, XTAL1, RPD) Input Hysteresis RSTIN, EA, NMI Input Hysteresis XTAL1 Input Hysteresis READY (TTL only) Input Hysteresis RPD Output low voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTIN, RSTOUT) Output low voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output low voltage RPD Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) Output high voltage(2) (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) Output high voltage RPD Input leakage current (P5[15:0])(3) Input leakage current (all except P5[15:0], P2[0], RPD, P3[12], P3[15]) VIH2 VIH3 VHYS
VHYSS CC VHYS1 CC VHYS2 CC VHYS3 CC VHYS4 CC
(1) (1) (1) (1) (1)
VOL
CC
-
V
IOL = 8mA IOL = 1mA
VOL1
CC
-
0.4 0.05 VDD 0.5 VDD 0.3 VDD -
V
IOL1 = 4mA IOL1 = 0.5mA IOL2 = 85A IOL2 = 80A IOL2 = 60A IOH = - 8mA IOH = - 1mA
VOL2
CC
-
V
VOH
CC
VDD - 0.8 VDD - 0.08
V
VOH1
CC
VDD - 0.8 VDD - 0.08 0 0.3 VDD 0.5 VDD - -
-
V
IOH1 = - 4mA IOH1 = - 0.5mA IOH2 = - 2mA IOH2 = - 750A IOH2 = - 150A - -
VOH2 |IOZ1 | |IOZ2 |
CC CC CC
- 0.2 0.5
V A A
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ST10F272M Table 56. DC characteristics (continued)
Limit values Parameter Symbol Min Input leakage current (P2[0])(4) Input leakage current (RPD) Input leakage current (P3[12], P3[15]) Overload current (all except P2[0]) Overload current (P2[0])(4) RSTIN pull-up resistor Read/Write inactive current(6)(7) Read/Write active current ALE inactive current(6)(7)
(6)(8) (6)(8)
Electrical characteristics
Unit Max +1.0 -0.5 3.0 1.0 5 +5 -1 250 -40 - - 300 -40 - -10 - 10 15 + 1.5 fCPU 15 + 1.5 fCPU 15 + 0.6 fCPU 200 400 Typical Value 200 A A A mA mA k A A A A A A A A pF mA mA mA
Test condition
|IOZ3 | |IOZ4 | |IOZ5 | |IOV1 | |IOV2 | RRST IRWH IRWL IALEL IALEH IP6H IP6L IP0H(6) IP0L(7)
CC CC CC SR SR CC
- - - - - 50 - -500 20 - - -500 - -100
- - -
(1)(5) (1)(5)
100 k nominal VOUT = 2.4V VOUT = 0.4V VOUT = 0.4V VOUT = 2.4V VOUT = 2.4V VOUT = 0.4V VIN = 2.0V VIN = 0.8V
(1)(6)
ALE active current
Port 6 inactive current (P6[4:0])(6)(7) Port 6 active current (P6[4:0])
(6)(8)
PORT0 configuration current(6)
Pin Capacitance (Digital inputs / outputs) CIO Run Mode Power supply current(9) (Execution from Internal RAM) Run Mode Power supply current(1)(10) (Execution from Internal Flash) Idle mode supply current(11) Power-down supply current(12) (RTC off, Oscillators off, Main Voltage Regulator off) Power-down supply current(12) (RTC on, Main Oscillator on, Main Voltage Regulator off) Power-down supply current(12) (RTC on, 32 kHz Oscillator on, Main Voltage Regulator off) Stand-by supply current(12) (RTC off, Oscillators off, VDD off, VSTBY on) ICC1 ICC2 IID
CC
- - - -
- - -
IPD1
-
A
TA = 25C
IPD2
-
A
TA = 25C
IPD3
-
A
TA = 25C VSTBY = 5.5V TA = TJ = 25C VSTBY = 5.5V TA = TJ = 125C
- ISB1 -
120 500
A A
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Electrical characteristics Table 56. DC characteristics (continued)
Limit values Parameter Symbol Min Stand-by supply current(12) (RTC on, 32 kHz Oscillator on, main VDD off, VSTBY on) Stand-by supply current(1)(12) (VDD transient condition) - ISB2 - ISB3 - 500 2.5 A mA Max 120 A Unit
ST10F272M
Test condition VSTBY = 5.5V TA = TJ = 25C VSTBY = 5.5V TA = TJ = 125C -
1. Not 100% tested, guaranteed by design characterization. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is imposed by the external circuitry. 3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default, after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins. 4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes) implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits: failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 37 for a scheme of the input circuitry. 5. Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the specified range (that is, VOV > VDD + 0.3V or VOV < -0.3V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits. 6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 7. The maximum current may be drawn while the respective signal line remains inactive. 8. The minimum current must be drawn in order to drive the respective signal line active. 9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is doing the following: Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules Watchdog Timer is enabled and regularly serviced RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6) ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 All interrupts generated by XPWM, RTC, Timers and ADC are not serviced 10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is doing the following: - Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM - Watchdog Timer is enabled and regularly serviced - RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles - Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling - Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6) - ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 - All interrupts generated by XPWM, RTC, Timers and ADC are not serviced 11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min. 12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0V to 0.1V or at VDD - 0.1V to VDD, VAREF = 0V, all outputs (including pins configured as outputs) disconnected. Also, the Main Voltage Regulator is assumed to be off; if it is not, an additional 1mA must be added.
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ST10F272M Figure 37. Port2 test mode structure
Electrical characteristics
Output buffer Clock
P2.0 CC0IO
Alternate data input Fast external interrupt input
Input latch
Test mode Flash sense amplifier and column decoder
Figure 38. Supply current versus the operating frequency (RUN and IDLE modes)
150
ICC1 = ICC2 100 I [mA]
50
IID
0
0
10
20
30 40 fCPU [MHz]
50
60
70
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Electrical characteristics
ST10F272M
24.6
Table 57.
Flash characteristics
VDD = 5V 10%, VSS = 0V Flash characteristics
Typical Parameter TA = 25C 0 cycles(1) Maximum TA = 125C 0 cycles(1) 80 150 2.0 0.9 0.8 2.0 1.8 3.7 3.3 13.6 11.9 40 10 30 20 90 100k cycles 290 570 3.9 1.0 0.9 2.7 2.5 5.1 4.7 19.2 17.5 40 10 30 20 300 s s s s s s s s s s ms s - - - not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed not preprogrammed preprogrammed
(4)
Unit
Notes
Word Program (32-bit) (2) Double Word Program (64-bit) Bank 0 Program (256 Kbyte) (Double Word Program) Sector Erase (8 Kbyte) Sector Erase (32 Kbyte) Sector Erase (64 Kbyte) Bank 0 Erase (256 Kbyte)(3) Recovery from Power-Down (tPD) Program Suspend Latency(4) Erase Suspend Latency
(4) (2)
35 60 1.6 0.6 0.5 1.1 0.8 1.7 1.3 5.6 4.0 - - - 20 40
- - Minimum delay between two requests -
Erase Suspend Request Rate(4) Set Protection(4)
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer). 2. Word and Double Word Programming times are provided as average values derived from a full sector programming time: absolute value of a Word or Double Word Programming time could be longer than the average value. 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As ST10F272M implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations. 4. Not 100% tested, guaranteed by Design Characterization.
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ST10F272M Table 58. Flash data retention characteristics
Electrical characteristics
Number of program / erase cycles (-40C < TA < 125C) 0 - 100 1000 10000 100000
Data retention time (average ambient temperature 60C) 256 Kbyte (code store) > 20 years 64 Kbyte (EEPROM emulation)(1) > 20 years > 20 years 10 years 1 year
1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbytes of EEPROM. Therefore, in case of an emulation of a 16 Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document (AN2061 - "EEPROM Emulation with ST10F2xx"). Contact your local field service, local sales person or STMicroelectronics representative to obtain a copy of such a guideline document.
24.7
A/D converter characteristics
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, 4.5V VAREF VDD, VSS VAGND VSS + 0.2V
Table 59.
A/D converter characteristics
Limit values Parameter Symbol Min Max VDD VSS + 0.2 VAREF 5 1 - - +1 +1.5 +1.5 +2.0 +5.0 +7.0 10-6 3 4 6 3.5 V V V mA A s s LSB LSB LSB LSB - pF pF pF Port5 Port1 Running mode(3) Power-down mode
(4) (5)
Unit 4.5 VSS VAGND - - 1 3 -1 -1.5 -1.5 -2.0 -5.0 -7.0 - - - -
Test condition
Analog Reference voltage(1) Analog Ground voltage Analog Input voltage
(2)
VAREF SR VAGND SR VAIN IAREF tS tC DNL INL OFS TUE K CP1 SR CC CC CC CC CC CC CC CC CC CC CC
Reference supply current Sample time Conversion time Differential Non Linearity(6) Integral Non Linearity Offset Error(6) Total unadjusted error(6) Coupling Factor between inputs(3)(7) Capacitance(3)(8)
(6)
No overload No overload No overload Port5 Port1 - No overload(3) Port1 - Overload(3) On both Port5 and Port1
Input Pin
CP2 Sampling Capacitance(3)(8) CS
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Electrical characteristics Table 59. A/D converter characteristics (continued)
Limit values Parameter Symbol Min RSW RAD CC CC - - - Max 600 1600 1300 W W Port5 Port1 Unit
ST10F272M
Test condition
Analog Switch Resistance(3)(8)
1. VAREF can be tied to ground when A/D Converter is not in use: There is increased consumption (approximately 200A) on main VDD due to internal analog circuitry not being completely turned off. Therefore, it is suggested to maintain the VAREF at VDD level even when not in use, and to eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register. 2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000H or 0x3FFH, respectively 3. Not 100% tested, guaranteed by design characterization 4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming and can be taken from Table 60: A/D converter programming. 5. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the next Table 60. 6. DNL, INL, OFS and TUE are tested at VAREF = 5.0V, VAGND = 0V, VDD = 5.0V. It is guaranteed by design characterization for all other voltages within the defined voltage range. `LSB' has a value of VAREF/1024. For Port5 channels, the specified TUE ( 2LSB) is guaranteed also with an overload condition (see IOV specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10mA. For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10mA (either dynamic or static injection), the specified TUE is degraded ( 7LSB). To obtain the same accuracy, the negative injection current on Port1 pins must not exceed -1mA in case of both dynamic and static injection. 7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges (for both positive and negative injection current). 8. Refer to scheme shown in Figure 40.
24.7.1
Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the ADC. During these steps the internal capacitances are repeatedly charged and discharged via the VAREF pin. The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F272M relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjustment of the ST10F272M A/D converter to the system's properties:
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ST10F272M
Electrical characteristics Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however. The conversion times are programmed via the upper four bits of register ADCON. Bit fields ADCTC and ADSTC are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. The table below lists the possible combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register.
Table 60.
ADCTC 00 00 00 00 11 11 11 11 10 10 10 10
A/D converter programming
ADSTC 00 01 10 11 00 01 10 11 00 01 10 11 Sample TCL * 120 TCL * 140 TCL * 200 TCL * 400 TCL * 240 TCL * 280 TCL * 400 TCL * 800 TCL * 480 TCL * 560 TCL * 800 TCL * 1600 Comparison TCL * 240 TCL * 280 TCL * 280 TCL * 280 TCL * 480 TCL * 560 TCL * 560 TCL * 560 TCL * 960 TCL * 1120 TCL * 1120 TCL * 1120 Extra TCL * 28 TCL * 16 TCL * 52 TCL * 44 TCL * 52 TCL * 28 TCL * 100 TCL * 52 TCL * 100 TCL * 52 TCL * 196 TCL * 164 Total conversion TCL * 388 TCL * 436 TCL * 532 TCL * 724 TCL * 772 TCL * 868 TCL * 1060 TCL * 1444 TCL * 1540 TCL * 1732 TCL * 2116 TCL * 2884
Note:
The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85s (see ST10F269).
24.7.2
A/D conversion accuracy
The A/D Converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The absolute accuracy of the A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors:

Offset error (OFS) Gain Error (GE) Quantization error Non-Linearity error (Differential and Integral)
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Electrical characteristics These four error quantities are explained below using Figure 39.
ST10F272M
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 39, see OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF, once offset error is subtracted. Gain error combined with offset error represents the so-called full-scale error (Figure 39, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
Non-linearity error
Non-Linearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see Figure 39):

Differential Non-Linearity error is the actual step dimension versus the ideal one (1 LSBIDEAL). Integral Non-Linearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. Note that for Integral NonLinearity error, the effect of offset, gain and quantization errors is not included.
Note:
Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the real characteristic, and 1/2 LSB after the last step again of the real characteristic.
24.7.3
Total unadjusted error
The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic: the number provided in the Data Sheet represents the maximum error with respect to the entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the Offset and Gain errors. Refer to Figure 39, see TUE.
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ST10F272M Figure 39. A/D conversion characteristics
Electrical characteristics
Offset Error OFS 3FF 3FE (6) 3FD Ideal Characteristic 3FC 3FB 3FA (2) Digital Out (HEX)
Gain Error GE
Bisector Characteristic
007 006 005
(7)
(1)
(5) 004 003 002 001 000 1 2 3 4 5 6 1 LSB (ideal) (4) (3)
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Non-Linearity Error (DNL) (4) Integral Non-Linearity Error (INL) (5) Center of a step of the actual transfer curve (6) Quantization Error (1/2 LSB) (7) Total Unadjusted Error (TUE)
Offset Error OFS
7 1018 1020 VAIN (LSBIDEAL) [LSBIDEAL = VAREF / 1024]
1022
1024
24.7.4
Analog reference pins
The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. A low pass filter on the A/D converter reference source (supplied through pins VAREF and VAGND), is recommended in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be sufficient in most of the cases; in presence of high RF noise energy, inductors or ferrite beads may be necessary. In this architecture, VAREF and VAGND pins represents also the power supply of the analog circuitry of the A/D converter: there is an effective DC current requirement from the reference voltage by the internal resistor string in the R-C DAC array and by the rest of the analog circuitry. An external resistance on VAREF could introduce error under certain conditions: for this reasons, series resistance are not advisable, and more in general any series devices in the filter network should be designed to minimize the DC resistance.
Analog Input pins
To improve the accuracy of the A/D converter, it is definitively necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; moreover, it sources charge during the sampling phase, when the analog signal source is a high-impedance source.
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A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth). Figure 40. A/D converter input pins scheme
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
VDD
Source
RS
Filter
RF
Current Limiter
RL
Channel Selection
RSW
Sampling
RAD
VA
CF
CP1
CP2
CS
RS RF CF RL RSW RAD CP CS
Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance Sampling Switch Impedance Pin Capacitance (two contributions, CP1 and CP2) Sampling Capacitance
Input Leakage and external circuit
The series resistor utilized to limit the current to a pin (see RL in Figure 40), in combination with a large source impedance can lead to a degradation of A/D converter accuracy when input leakage is present. Data about maximum input leakage current at each pin is provided in the Data Sheet (Electrical Characteristics section). Input leakage is greatest at high operating temperatures, and in general it decreases by one half for each 10 C decrease in temperature. Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF = 5V), an input leakage of 100nA acting though an RL = 50k of external resistance leads to an error of exactly one count (5mV); if the resistance were 100k the error would become two counts. Eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the A/D converter measurements. Another contribution to the total leakage is represented by the charge sharing effects with the sampling capacitance: being CS substantially a switched capacitance, with a frequency equal to the conversion rate of a single channel (maximum when fixed channel continuous conversion mode is selected), it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 250 kHz, with CS equal to 4pF, a resistance of 1M is obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance
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ST10F272M
Electrical characteristics (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the following relation:
R S + R F + R L + R SW + R AD -1 V A ----------------------------------------------------------------------------- < -- LSB R EQ 2
The formula above provides constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network must be considered. Assuming the three capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the equivalent circuit shown in Figure 40), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. Figure 41. Charge sharing timing diagram during sampling phase
VCS VA VA2 1
Voltage Transient on CS V < 0.5 LSB 2 1 < (RSW + RAD) CS << TS
VA1
2 = RL (CS + CP1 + CP2)
TS
t
In particular two different transient periods can be distinguished (see Figure 41):
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is shown in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS are in series, and the time constant is:
CP CS 1 = ( R SW + R AD ) ---------------------CP + CS
This relation can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D Converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant:
1 < ( R SW + R AD ) C S < < T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to the following equation:
V A1 ( C S + C P1 + C P2 ) = V A ( C P1 + C P2 )
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A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is:
2 < R L ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraint on RL sizing is obtained:
10 2 = 10 R L ( C S + C P1 + C P2 ) TS
Of course, RL must also be sized according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. The following equation must be respected (charge balance assuming now CS already charged at VA1):
VA2 ( C S + C P1 + C P2 + C F ) = V A C F + V A1 ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing (see Figure 42). Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. Figure 42. Anti-aliasing filter and conversion rate
Analog Source Bandwidth (VA) Noise TC 2 RFCF (Conversion Rate vs. Filter Pole) fF = f0 (Anti-aliasing Filtering Condition) 2 f0 fC (Nyquist)
f Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate)
f0
fF
f
f0
fC
f
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ST10F272M
Electrical characteristics The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive the following relation between the ideal and real sampled voltage on CS:
VA C P1 + C P2 + C F ----------- = -----------------------------------------------------------V A2 C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5V), assuming to accept a maximum error of half a count (~2.44mV), a constraint is immediately evident on CF value:
C F > 2048 C S
In the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making a hypothesis on the characteristics of the analog signal to be sampled.
Example of external network sizing
The following hypotheses are formulated in order to proceed in designing the external network on A/D Converter input pins:

Analog Signal Source Bandwidth (f0): 10 kHz conversion Rate (fC): 25 kHz Sampling Time (TS): 1s Pin Input Capacitance (CP1): 5pF Pin Input Routing Capacitance (CP2): 1pF Sampling Capacitance (CS): 4pF Maximum Input Current Injection (IINJ): 3mA Maximum Analog Source Voltage (VAM): 12V Analog Source Impedance (RS): 100 Channel Switch Resistance (RSW): 500 Sampling Switch Resistance (RAD): 200
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Electrical characteristics 1.
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Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is:
1 R C C F = ----------- = 15.9s 2f 0
2.
Using the relation between CF and CS and taking some margin (4000 instead of 2048), it is possible to define CF:
C F = 4000 C S = 16nF
3.
As a consequence of step 1 and 2, RC can be chosen:
1 R F = -------------------- = 995 1k 2f 0 C F
4.
Considering the current injection limitation and supposing that the source can go up to 12V, the total series resistance can be defined as:
V AM R S + R F + R L = ------------ = 4k I INJ
from which is now simple to define the value of RL:
V AM R L = ------------ - R F - R S = 2.9k I INJ
5.
Now the three elements of the external circuit RF, CF and RL are defined. Some conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. The relation which allows minimization of the accuracy error introduced by the switched capacitance equivalent resistance is in this case:
1 R EQ = -------------- = 10M fC CS
So the error due to the voltage partitioning between the real resistive path and CS is less then half a count (considering the worst case when VA = 5V):
R S + R F + R L + R SW + R AD 1 V A -------------------------------------------------------------------------- = 2.35mV < -- LSB 2 R EQ
The other condition to be verified is if the time constants of the transients are really and significantly shorter than the sampling period duration TS:
1 = ( R SW + R AD ) C S = 2.8ns << TS = 1s < TS = 1s
10 2 = 10 R L( C S + C P1 + C P2 ) = 290ns
For the complete set of parameters characterizing the ST10F272M A/D Converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page 131.
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Electrical characteristics
24.8
24.8.1
AC characteristics
Test waveforms
Figure 43. Input / output waveforms
2.4V 2.0V Test Points 0.4V 0.8V 0.8V 2.0V
AC inputs during testing are driven at 2.4V for a logic `1' and 0.4V for a logic `0'. Timing measurements are made at VIH min. for a logic `1' and VIL max for a logic `0'.
Figure 44. Float waveforms
VOH VLOAD + 0.1V VLOAD VLOAD - 0.1V VOH - 0.1V Timing Reference Points VOL + 0.1V VOL For timing purposes a port pin is no longer floating when VLOAD changes of 100mV. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).
24.8.2
Definition of internal timing
The internal operation of the ST10F272M is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example, pipeline) or external (for example, bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL". The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F272M. The example for PLL operation shown in Figure 45 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5).
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Electrical characteristics Figure 45. Generation mechanisms for the CPU clock
Phase locked loop operation fXTAL fCPU
TCLTCL
ST10F272M
Direct Clock Drive fXTAL fCPU
TCLTCL
Prescaler Operation fXTAL fCPU TCL TCL
24.8.3
Clock generation modes
The next Table 61 associates the combinations of these three bits with the respective clock generation mode. Table 61. On-chip clock generator selections
CPU frequency fCPU = fXTAL x F 1 0 1 0 1 0 1 0 fXTAL x 4 fXTAL x 3 fXTAL x 8 fXTAL x 5 fXTAL x 1 fXTAL x 10 fXTAL / 2 fXTAL x 16 External clock input range(1)(3) 4 to 8 MHz 5.3 to 8 MHz 4 to 8 MHz 6.4 to 8 MHz 1 to 64 MHz 4 to 6.4 MHz 4 to 8 MHz 4 MHz CPU clock via prescaler(3) Direct Drive (oscillator bypassed)(2) Notes Default configuration
P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0
1. The external clock input range refers to a CPU clock range of 1...40 MHz. Moreover, the PLL usage is limited to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can be used). 2. The maximum depends on the duty cycle of the external clock signal: when 40 MHz is used, 50% duty cycle is granted (low phase = high phase = 12.5ns); when 20 MHz is selected a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 12.5ns). 3. The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required. Also when the PLL is not used and the CPU clock corresponds to fXTAL/2, an external crystal or resonator must be used: It is not possible to force any clock though an external clock source.
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24.8.4
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal "001" during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (that is, the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
24.8.5
Direct drive
When pins P0.15-13 (P0H.7-5) equal "011" during reset the on-chip phase locked loop is disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL1 pin. The frequency of CPU clock (fCPU) directly follows the frequency of fXTAL so the high and low time of fCPU (that is, the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula:
TCL min = 1 f XTALl xlDC min DC = duty cycle
For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TCL = 1 f XTAL
The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
24.8.6
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F272M. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator). This watchdog oscillator operates as following. The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
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an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply current.
24.8.7
Phase Locked Loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and it provides the CPU clock (see Table 61). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU = fXTAL x F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to one TCL period. This is especially important for bus cycles using wait states and for example, such as for the operation of timers or serial interfaces. For all slower operations and longer periods (for example, pulse train generation or measurement, or lower baudrates) the deviation caused by the PLL jitter is negligible. Refer to next Section 24.8.9: PLL jitter for more details.
24.8.8
Voltage controlled oscillator
The ST10F272M implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following table gives a detailed summary of the internal settings and VCO frequency.
Table 62.
P0.15-13 (P0H.7-5) 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1
Internal PLL divider mechanism
XTAL frequency 4 to 8 MHz 5.3 to 10.6 MHz(1) Input prescaler fXTAL / 4 fXTAL / 4 fXTAL / 4 fXTAL / 4 - PLL Multiply by 64 48 64 40 Divide by 4 4 2 2 Output prescaler - - - - - CPU frequency fCPU = fXTAL x F fXTAL x 4 fXTAL x 3 fXTAL x 8 fXTAL x 5 fXTAL x 1
4 to 8 MHz 6.4 to 8 MHz
(1)
1 to 40 MHz
PLL bypassed
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ST10F272M Table 62.
P0.15-13 (P0H.7-5) 0 0 0 1 0 0 0 1 0
Electrical characteristics Internal PLL divider mechanism (continued)
XTAL frequency 4 MHz 4 to 8 MHz(1) Input prescaler fXTAL / 2 - PLL Multiply by 40 Divide by 2 Output prescaler - fPLL / 2 CPU frequency fCPU = fXTAL x F fXTAL x 10 fXTAL / 2
PLL bypassed -
1. The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 40 MHz.
Example 1

fXTAL = 4 MHz P0(15:13) = `110' (multiplication by 3) PLL input frequency = 1 MHz VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz fCPU = NOT VALID
Example 2

fXTAL = 8 MHz P0(15:13) = `100' (multiplication by 5) PLL input frequency = 2 MHz VCO frequency = 80 MHz PLL output frequency = 40 MHz (VCO frequency divided by 2) fCPU = 40 MHz (no effect of Output Prescaler)
24.8.9
PLL jitter
The following terminology is hereafter defined:
Self referred single period jitter Also called "Period Jitter", it can be defined as the difference of the Tmax and Tmin, where Tmax is maximum time period of the PLL output clock and Tmin is the minimum time period of the PLL output clock. Self referred long term jitter Also called "N period jitter", it can be defined as the difference of Tmax and Tmin, where Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the minimum time difference between N+1 clock rising edges. Here N should be kept sufficiently large to have the long term jitter. For N=1, this becomes the single period jitter. Jitter in the input clock Noise in the PLL loop
Jitter at the PLL output can be due to the following reasons:

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Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:

Device noise of the circuit in the PLL Noise in supply and substrate.
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider the loop bandwidth is, the lower the jitter is due to noise in the loop. Moreover, the long term jitter is practically independent of the multiplication factor. The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled Oscillator). There are two main sources of noise: thermal (random noise, frequencyindependent noise, thus, practically white noise) and flicker (low frequency noise, 1/f). For the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f2 region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a noiseless PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S. value of the accumulated jitter is proportional to the square root of N, where N is the number of clock periods within the considered time interval. On the contrary, assuming again a noiseless PLL input and supposing that the VCO is dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N, where N is the number of clock periods within the considered time interval. The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller than a certain value depending on the PLL output frequency and on the bandwidth characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise component. Lastly, for N greater than a second value of N, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods N). The PLL loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation value corresponds to what has been called self referred long term jitter of the PLL. In Figure 46 the maximum jitter trend versus the number of clock periods N (for some typical CPU frequencies) is shown: The curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations: The real jitter is always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent of the multiplication factor. Its effects are strongly reduced thanks to the particular care used in the physical implementation and integration of the PLL module inside the device. Nonetheless, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure 46.
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ST10F272M Figure 46. ST10F272M PLL jitter
5 16MHz 24MHz 32MHz 40MHz 4
Electrical characteristics
64MHz
Jitter [ns]
3
2
1 TJIT 0 0 200 400 1000 600 800 N (CPU clock periods) 1200 1400
24.8.10
PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a backup clock signal (free running frequency ffree). This feature allows recovery from a crystal failure occurrence without risking to go into an undefined configuration: The system is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe mode. The path between reference clock and PLL input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
Note:
The external RC circuit on RSTIN pin must be properly sized in order to extend the duration of the low pulse to lock the PLL before the level at RSTIN pin is recognized high: A bidirectional reset internally drives the RSTIN pin low for just 1024 TCL (definitly not sufficient to lock the PLL starting from free-running mode). Table 63.
Symbol tPSUP tLOCK TJIT ffree
PLL characteristics (VDD = 5V 10%, VSS = 0V, TA = -40 to +125C)
Value Parameter PLL Start-up time(1) PLL Lock-in time Single Period Jitter(1) (cycle to cycle = 2 TCL) PLL free running frequency Multiplication factors: 5, 8, 10, 16 500 4000 Conditions Min Stable VDD and reference clock Stable VDD and reference clock, starting from free-running mode 6 sigma time period variation (peak to peak) Multiplication factors: 3, 4 - - -500 250 Max 300 250 +500 2000 kHz s s ps Unit
1. Not 100% tested, guaranteed by design characterization
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24.8.11
Main oscillator specifications
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C Table 64.
Symbol
Main oscillator characteristics
Value Parameter Oscillator Transconductance Oscillation Amplitude(1) Oscillation Voltage level
(1)
Conditions Min Typ 2.6 1.5 0.8 6 1 Max 4.2 - - 10 2
Unit
gm VOSC VAV tSTUP
1.4 Peak to Peak Sine wave middle Stable VDD - Crystal Stable VDD - Resonator - - - -
mA/V V V ms ms
Oscillator Start-up Time(1)
1. Not 100% tested, guaranteed by design characterization
Figure 47. Crystal oscillator and resonator connection diagram
ST10F272M XTAL1 XTAL2 XTAL1 ST10F272M XTAL2 Resonator CA = 35pF Max - - Min 430 120 Typ 850 250 Max - -
Crystal
CA
CA
Table 65.
Main oscillator negative resistance (module)
CA = 15pF Min Typ 1035 450 Max - - Min 550 170 CA = 25pF Typ 1050 350
4 MHz 8 MHz
545 240
The given values of CA do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C0) and the package capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 10pF. The external resistance between XTAL1 and XTAL2 is not necessary, since already present on the silicon.
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Electrical characteristics
24.8.12
32 kHz oscillator specifications
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C Table 66.
Symbol
32 kHz oscillator characteristics
Value Parameter Conditions Min Typ 31 17 1.0 0.9 1 Max 50 30 2.4 1.2 5 A/V A/V V V s Start-up Normal run Peak to Peak Sine wave middle Stable VDD 20 8 0.5 0.7 - Unit
gm32
Oscillator Transconductance(1)
VOSC32 Oscillation Amplitude(2) VAV32 Oscillation Voltage level(2)
tSTUP32 Oscillator Start-up Time(2)
1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started, the current biasing is reduced to lower the power consumption of the system. 2. Not 100% tested, guaranteed by design characterization.
Figure 48. 32 kHz crystal oscillator connection diagram
ST10F272M XTAL3 XTAL4 Crystal CA CA -
Table 67.
Frequency 32 kHz
Minimum values of negative resistance (module) for 32 kHz oscillator
CA = 6pF CA = 12pF CA = 15pF CA = 18pF CA = 22pF CA = 27pF CA = 33pF 150 k 120 k 90 k
The given values of CA do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C0) and the package capacitance between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon.
Warning:
Direct driving on XTAL3 pin is not supported. Always use a 32 kHz crystal oscillator.
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24.8.13
External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that targets a maximum CPU frequency of 40 MHz. In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when the on-chip oscillator is enabled it is forbidden to use any external clock source different from crystal or ceramic resonator. Table 68. External clock drive
Direct drive fCPU = fXTAL Min XTAL1 period(1)(2) tOSC SR High time(3)
(3)
Parameter
Symbol
Direct drive with prescaler fCPU = fXTAL / 2 Min 83.3 3 3 - - Max 250 - - 2 2
PLL usage fCPU = fXTAL x F Min 83.3 6 6 - - Max 250 - - 2 2
Unit
Max - - - 2 2
25 6 6 - -
ns ns ns ns ns
t1 t2 t3 t4
SR SR SR SR
Low time
Rise time(3) Fall time(3)
1. The minimum value for the XTAL1 signal period is considered the theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. 4 to 8 MHz is the input frequency range when using an external clock source. 40 MHz can be applied with an external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is bypassed so it does not limit the input frequency. 3. The input clock signal must reach the defined levels VIL2 and VIH2.
Figure 49. External clock drive XTAL1
t1 VIH2 VIL2 t2 tOSC t3 t4
Note:
When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: When 40 MHz is used, 50% duty cycle is granted (low phase = high phase = 12.5ns); when for instance 20 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 12.5ns).
24.8.14
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes how these variables are to be computed.
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ST10F272M Table 69. Memory cycle variables
Description ALE Extension Memory Cycle Time wait states Memory Tri-state Time Symbol tA tC tF
Electrical characteristics
Values TCL x [ALECTL] 2TCL x (15 - [MCTC]) 2TCL x (1 - [MTTC])
24.8.15
External memory bus timing
The following sections include the External Memory Bus timings. The given values are computed for a maximum CPU clock of 40 MHz.
Note:
All External Memory Bus Timings and SSC Timings listed in the following tables are granted by Design Characterization and not fully tested in production.
24.8.16
Multiplexed bus
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, CL = 50pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40 MHz CPU clock without wait states)
Table 70.
Symbol
Multiplexed bus timings
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max - - - - - 6 18.5 - - 6 + tC 18.5 + tC 17.5 + + tA + tC Variable CPU clock 1/2 TCL = 1 to 40 MHz Min TCL - 8.5 + tA TCL - 11 + tA TCL - 8.5 + tA TCL - 8.5 + tA - 8.5 + tA - - 2TCL - 9.5 + tC 3TCL - 9.5 + tC - - - Max - - - - - 6 TCL + 6 - - 2TCL - 19 + tC 3TCL - 19 + tC 3TCL - 20 + + tA + tC ns ns ns ns ns ns ns ns ns ns ns ns Unit
t5 t6 t7 t8 t9
CC CC CC tCC CC
ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay)1 Address float after RD, WR (no RW-delay)1 RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in
4 + tA 1.5 + tA 4 + tA 4 + tA - 8.5 + tA - - 15.5 + tC 28 + tC - - -
t10 CC t11 CC t12 CC t13 CC t14 SR t15 SR t16 SR
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Electrical characteristics Table 70.
Symbol
ST10F272M
Multiplexed bus timings (continued)
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max 20 + 2tA + + tC - 16.5 + tF - - - - 10 - tA 16.5 + tC + + 2tA - - - 1.5 14 4 + tC 16.5 + tC - - - - 16.5 + tF - - Variable CPU clock 1/2 TCL = 1 to 40 MHz Min - 0 - 2TCL - 15 + tC 2TCL - 8.5 + tF 2TCL - 10 + tF 2TCL - 15 + tF - 4 - tA - 3TCL - 10.5 + tF TCL - 5.5 + tA -5.5 + tA - - - - 2TCL - 9.5 + tC 3TCL - 9.5 + tC 2TCL - 15 + tC 0 - 2TCL - 19 + tF 2TCL - 19 + tF Max 4TCL - 30 + + 2tA + tC - 2TCL - 8.5 + tF - - - - 10 - tA 3TCL - 21 + + tC + 2tA - - - 1.5 TCL + 1.5 2TCL - 21 + tC 3TCL - 21 + tC - - - - 2TCL - 8.5 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t17 SR t18 SR t19 SR t22 CC t23 CC t25 CC t27 CC t38 CC t39 SR t40 CC t42 CC t43 CC t44 CC t45 CC t46 SR t47 SR t48 CC t49 CC t50 CC t51 SR t52 SR t54 CC t56 CC
Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD1 Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR ALE falling edge to Latched CS Latched CS low to Valid Data In Latched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay)1 Address float after RdCS, WrCS (no RW delay)1 RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS1 Address hold after RdCS, WrCS Data hold after WrCS
- 0 - 10 + tC 4 + tF 15 + tF 10 + tF - 4 - tA - 27 + tF 7 + tA -5.5 + tA - - - - 15.5 + tC 28 + tC 10 + tC 0 - 6 + tF 6 + tF
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ST10F272M
Electrical characteristics
Figure 50. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE
CLKOUT
t5 ALE t6 t38
t16
t25
t17
t40 t39 t27
CSx t6 A23-A16 (A15-A8) BHE t17 Address
t27
t16 Read cycle Address/data bus (P0) t6 Address t7 t1 Data in Address
t8 RD
t10 t14 t12 t13
t19
t9
t1 t15 t23
Write cycle Address/data bus (P0) Address
Data out
t8 WR WRL WRH t9 t13
t22
t12
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Electrical characteristics
ST10F272M
Figure 51. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE
CLKOUT t16
t5 ALE t6 t38 t17 CSx t6 A23-A16 (A15-A8) BHE t17
t25
t40 t39 t27
Address t27
Read cycle Address/Data Bus (P0)
t6 Address
t7 Data in t18 t19 t14
t8 t9 RD
t10 t11
t15 t12 t13 Write cycle Address/Data Bus (P0) Address Data out t23 t8 WR WRL WRH t9 t10 t11
t22
t13
t12
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ST10F272M
Electrical characteristics
Figure 52. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT t5 ALE t16 t25
t6 A23-A16 (A15-A8) BHE
t17
Address
t27
t16 t6 Read Cycle Address/Data Bus (P0)
Address
t7
t51
Data In Address
t42
t44 t46
t52
RdCSx
t48 t49 t43 t45 t47 t55
Data Out
Write Cycle Address/Data Bus (P0)
Address
t42 WrCSx
t50
t43 t49
t48
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Electrical characteristics
ST10F272M
Figure 53. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS
CLKOUT t16
t5 ALE t6 A23-A16 (A15-A8) BHE t17
t25
Address t54
Read cycle Address/Data Bus (P0)
t6 Address
t7 Data in t42 t43 t45 t46 t44 t18 t19
RdCSx t47 t49
t48
Write cycle Address/data bus (P0)
Address
Data out
t42 t43 WrCSx t45
t44 t50
t56
t48 t49
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ST10F272M
Electrical characteristics
24.8.17
Demultiplexed bus
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, CL = 50pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40 MHz CPU clock without wait states).
Table 71.
Symbol
Demultiplexed bus timings
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max - - - Variable CPU clock 1/2 TCL = 1 to 40 MHz Min TCL - 8.5 + tA TCL - 11 + tA 2TCL - 12.5 + + 2tA Max - - - ns ns ns Unit
.
t5 t6 t80
CC ALE high time CC Address setup to ALE Address/Unlatched CS setup CC to RD, WR (with RW-delay) Address/Unlatched CS setup CC to RD, WR (no RW-delay) CC CC SR SR RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay)
4 + tA 1.5 + tA 12.5 + 2tA
t81
0.5 + 2tA
-
TCL - 12 + 2tA
-
ns
t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26 t28
15.5 + tC 28 + tC - - - - 0 - - 10 + tC 4 + tF -10 + tF 0 + tF -5 + tF -4 - tA
- - 6 + tC 18.5 + tC 17.5 + tA + + tC 20 + 2tA + + tC - 16.5 + tF 4 + tF - - - - - 6 - tA
2TCL - 9.5 + tC 3TCL - 9.5 + tC - - - - 0 - - 2TCL - 15 + tC TCL - 8.5 + tF -10 + tF 0 + tF -5 + tF -4 - tA
- - 2TCL - 19 + tC 3TCL - 19 + tC 3TCL - 20 + + tA + tC 4TCL - 30 + + 2tA + tC - 2TCL - 8.5 + + tF + 2tA TCL - 8.5 + + tF + 2tA - - - - - 6 - tA
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SR ALE low to valid data in SR SR SR SR Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay)(1) Data float after RD rising edge (no RW-delay)(1)
CC Data valid to WR CC Data hold after WR CC ALE rising edge after RD, WR CC Address/Unlatched CS hold after RD, WR(2) Address/Unlatched CS hold after WRH ALE falling edge to Latched CS
t28h CC t38 CC
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Electrical characteristics Table 71.
Symbol
ST10F272M
Demultiplexed bus timings (continued)
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max 16.5 + + tC + 2tA - Variable CPU clock 1/2 TCL = 1 to 40 MHz Min - TCL - 10.5 + tF Max 3TCL - 21 + + tC + 2tA - ns ns Unit
t39 t41
SR CC
Latched CS low to Valid Data In Latched CS hold after RD, WR
- 2 + tF
t82
Address setup to RdCS, CC WrCS (with RW-delay) Address setup to RdCS, CC WrCS (no RW-delay) SR SR CC CC RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay)
14 + 2tA
-
2TCL - 11 + 2tA
-
ns
t83
2 + 2tA
-
TCL - 10.5 + 2tA
-
ns
t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
- - 15.5 + tC 28 + tC 10 + tC 0 - - -8.5 + tF 2 + tF
4 + tC 16.5 + tC - - - - 16.5 + tF 4 + tF - -
- - 2TCL - 9.5 + tC 3TCL - 9.5 + tC 2TCL - 15 + tC 0 - - -8.5 + tF TCL - 10.5 + tF
2TCL - 21 + tC 3TCL - 21 + tC - - - - 2TCL - 8.5 + tF TCL - 8.5 + tF - -
ns ns ns ns ns ns ns ns ns ns
CC Data valid to WrCS SR Data hold after RdCS SR SR CC Data float after RdCS (with RW-delay)(3) Data float after RdCS (no RW-delay)(3) Address hold after RdCS, WrCS
CC Data hold after WrCS
1. RW-delay and tA refer to the next following bus cycle. 2. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3. Partially tested, guaranteed by design characterization.
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ST10F272M
Electrical characteristics
Figure 54. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE
CLKOUT t5 ALE t6 t38
t17
t9
t26
t41 t39 t41u
CSx t6 A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 t80 t81 RD t12 t13 Write cycle Data bus (P0) (D15-D8) D7-D0 t80 t81 WR WRL WRH t13 Data out t14 t15
t17 Address
t28 (or t28h)
t18 Data in t20 t21
t22
t24
t12
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Electrical characteristics
ST10F272M
Figure 55. External memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE
CLKOUT
t5 t16
t26
ALE t6 t38 t17 t39 CSx t6 A23-A16 A15-A0 (P1) BHE t17 t28 t28 t41
Address t18
Read cycle Data bus (P0) (D15-D8) D7-D0 t80 t81 t14 t15
Data in t20 t21
RD t12 t13 Write cycle Data bus (P0) (D15-D8) D7-D0 t80 t81 WR WRL WRH t13 t22 t24 Data out
t12
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ST10F272M
Electrical characteristics
Figure 56. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS
CLKOUT t5 ALE t16 t26
t6 t17 A23-A16 A15-A0 (P1) BHE Address
t55
Read cycle Data bus (P0) (D15-D8) D7-D0 t82 t83 t46 t47
t5 Data in t53 t68
RdCSx t48 t49 Write cycle Data bus (P0) (D15-D8) D7-D0 t82 t83 WrCSx t48 t49
Data out
t50
t57
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Electrical characteristics
ST10F272M
Figure 57. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS
CLKOUT t5 ALE t6 A23-A16 A15-A0 (P1) BHE t16 t26
t17 Address
t55
Read cycle Data bus (P0) (D15-D8) D7-D0 t82 t83 t47 t46
t51 Data in t53 t68
RdCSx t48 t49 Write cycle Data bus (P0) (D15-D8) D7-D0 t82 t83 t50 t57
Data out
WrCSx t48 t49
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ST10F272M
Electrical characteristics
24.8.18
CLKOUT and READY
VDD = 5V 10%, VSS = 0V, TA = -40 to + 125C, CL = 50pF
Table 72.
Symbol
CLKOUT and READY timings
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max 25 - - 4 4 8 + tA - - - - - 2tA + tC + tF Variable CPU clock 1/2 TCL = 1 to 40 MHz Min 2TCL TCL - 3.5 TCL - 2.5 - - -2 + tA 17 2 2TCL + 10 17 2 0 Max 2TCL - - 4 4 8 + tA - - - - - 2tA + tC + tF ns ns ns ns ns ns ns ns ns ns ns ns Unit
t29 CC CLKOUT cycle time t30 CC CLKOUT high time t31 CC CLKOUT low time t32 CC CLKOUT rise time t33 CC CLKOUT fall time t34 CC CLKOUT rising edge to ALE falling edge t35 SR t36 SR Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT
25 9 10 - - -2 + tA 17 2 35 17 2 0
t37 SR Asynchronous READY low time t58 SR Asynchronous READY setup time(1) t59 SR Asynchronous READY hold time(1) t60 SR Asynchronous READY hold time after RD, WR high (Demultiplexed Bus)(2)
1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
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Electrical characteristics Figure 58. CLKOUT and READY
READY wait state
ST10F272M
Running cycle 1)
t32 t30 t34 t31 t33 t29
MUX / Tri-state 6)
CLKOUT
ALE
7)
RD, WR Synchronous READY Asynchronous READY
t58
3)
2)
t35
t36
t35
3)
t36
3)
t59
t58
3)
t59
t60 4)
t37
5)
6)
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here.
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ST10F272M
Electrical characteristics
24.8.19
External bus arbitration
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, CL = 50pF Table 73.
Symbol
External bus arbitration timings
Parameter fCPU = 40 MHz TCL = 12.5ns Min Max - 12.5 12.5 20 15 20 15 Variable CPU clock 1/2 TCL = 1 to 40 MHz Min 18.5 - - - -4 - -4 Max - 12.5 12.5 20 15 20 15 ns ns ns ns ns ns ns Unit
t61 SR t62 CC t63 CC
HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay
18.5 - - - -4
t64 CC CSx release(1) t65 CC CSx drive t66 CC Other signals release t67 CC Other signals drive
(1)
- -4
1. Partially tested, guaranteed by design characterization
Figure 59. External bus arbitration (releasing the bus)
CLKOUT t61 HOLD t63 HLDA BREQ t64 CSx (P6.x) 1) Others t66 1) t62 2) 3)
1. The ST10F272M will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64.
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Electrical characteristics Figure 60. External bus arbitration (regaining the bus)
(2)
ST10F272M
CLKOUT t61 HOLD t62 HLDA t62 BREQ t62
(1)
t63
t65 CSx (On P6.x) t67 Other signals
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F272M requesting the bus. 2. The next ST10F272M driven bus cycle may start here.
24.8.20
High-speed synchronous serial interface (SSC) timing
24.8.20.1 Master mode
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, CL = 50pF Table 74. SSC master mode timings
Maximum baudrate 6.6 Mbaud(1) @ fCPU = 40 MHz ( = 0002h) Min t300 t301 t302 t303 t304 t305 t306 CC SSC clock cycle time(2) CC SSC clock high time CC SSC clock low time CC SSC clock rise time CC SSC clock fall time CC Write data valid after shift edge CC Write data hold after shift edge(3) 150 63 63 - - - -2 Max 150 - - 10 10 15 - Variable baudrate ( = 0001h - FFFFh)
Symbol
Parameter
Unit
Min 8TCL t300 / 2 - 12 t300 / 2 - 12 - - - -2
Max 262144 TCL - - 10 10 15 - ns ns ns ns ns ns ns
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ST10F272M Table 74. SSC master mode timings (continued)
Maximum baudrate 6.6 Mbaud(1) @ fCPU = 40 MHz ( = 0002h) Min Read data setup time before latch t307p SR edge, phase error detection on (SSCPEN = 1) Read data hold time after latch t308p SR edge, phase error detection on (SSCPEN = 1) t307 Read data setup time before latch SR edge, phase error detection off (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off (SSCPEN = 0) 37.5 Max -
Electrical characteristics
Symbol
Parameter
Variable baudrate ( = 0001h - FFFFh)
Unit
Min 2TCL + 12.5
Max - ns
50
-
4TCL
-
ns
25
-
2TCL
-
ns
t308
0
-
0
-
ns
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud ( = `2h') due to the limited granularity of . Value `1h' for can be used only with CPU clock equal to (or lower than) 32 MHz. 2. Formula for SSC Clock Cycle time: t300 = 4 TCL x ( + 1) Where represents the content of the SSC baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125ns (corresponding to 8Mbaud). 3. Partially tested, guaranteed by design characterization.
Figure 61. SSC master timing
(1)
t300
t301
t302
(2)
SCLK t305 MTSR t304 t305 1st out bit t307 t308 MRST 1st in bit 2nd In bit t303 t306 t305 Last out bit t307 t308 Last in bit
2nd out bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
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Electrical characteristics
ST10F272M
24.8.20.2 Slave mode
VDD = 5V 10%, VSS = 0V, TA = -40 to +125C, CL = 50pF Table 75. SSC slave mode timings
Maximum baudrate 6.6 Mbaud(1) @ fCPU = 40 MHz ( = 0002h) Min t310 t311 t312 t313 t314 t315 t316 SR SSC clock cycle time(2) SR SSC clock high time SR SSC clock low time SR SSC clock rise time SR SSC clock fall time CC Write data valid after shift edge CC Write data hold after shift edge 150 63 63 - - - 0 62 Max 150 - - 10 10 55 - - Variable baudrate ( = 0001h - FFFFh)
Symbol
Parameter
Unit
Min 8TCL t310 / 2 - 12 t310 / 2 - 12 - - - 0 4TCL + 12
Max 262144 TCL - - 10 10 2TCL + 30 - - ns ns ns ns ns ns ns ns
Read data setup time before latch t317p SR edge, phase error detection on (SSCPEN = 1) Read data hold time after latch t318p SR edge, phase error detection on (SSCPEN = 1) t317 Read data setup time before latch SR edge, phase error detection off (SSCPEN = 0) Read data hold time after latch SR edge, phase error detection off (SSCPEN = 0)
87
-
6TCL + 12
-
ns
6
-
6
-
ns
t318
31
-
2TCL + 6
-
ns
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud ( = `2h') due to the limited granularity of . Value `1h' for may be used only with CPU clock lower than 32 MHz (after checking that resulting timings are suitable for the master). 2. Formula for SSC Clock Cycle time: t310 = 4 TCL * ( + 1) Where represents the content of the SSC baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).
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ST10F272M Figure 62. SSC slave timing
t310 t311 t312
Electrical characteristics
(1)
(2)
SCLK t314 t315 MRST t315 1st out bit t317 t318 MTSR 1st in bit 2nd in bit 2nd out bit t313 t316 t315 Last out bit t317 t318 Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
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Package information
ST10F272M
25
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK(R) specifications are available at www.st.com.
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ST10F272M Figure 63. PQFP144 mechanical data and package dimension
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 22.75 0.80 1.60 0(min.), 7(max.) 0.95 0.026 31.45 28.10 1.219 1.098 3.42 3.67 0.38 0.23 31.45 28.10 mm TYP. MAX. 4.07 0.010 0.125 0.009 0.005 1.219 1.098 1.228 1.102 0.896 0.026 1.228 1.102 0.896 0.031 0.063 0.037 1.238 1.106 0.135 0.144 0.015 0.009 1.238 1.106 MIN. inch TYP. MAX. 0.160
Package information
OUTLINE AND MECHANICAL DATA
PQFP144
D D1 A D3 A1 108 109 73 72
0.10mm .004 Seating Plane
A2
B
E3
E1
144 1 e 36
37 C
L1
E
L
K
PQFP144
B
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Package information Figure 64. LQFP144 mechanical data and package dimension
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 22.00 20.00 17.50 0.50 22.00 20.00 17.50 0.60 1.00 0.75 0.018 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.003 0.866 0.787 0.689 0.020 0.866 0.787 0.689 0.024 0.0393 0.030 0.055 0.009 MIN. TYP. MAX. 0.063 0.006 0.057 0.011 0.008 inch
ST10F272M
OUTLINE AND MECHANICAL DATA
3.5 (min.), 7(max.)
LQFP144 TQFP144 (20x20x1.40mm)
Note 1: Exact shape of each corner is optional.
0099183 B
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ST10F272M
Ordering information
26
Ordering information
Table 76. Device summary
Package Packing Tray PQFP144 ST10F272M-4QR3 ST10F272M-4T3 LQFP144 ST10F272M-4TR3 Tape and reel Tape and reel -40 to +125 Tray 1 to 40 Temperature range (C) CPU frequency range (MHz)
Order code ST10F272M-4Q3
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Revision history
ST10F272M
27
Revision history
Table 77.
Date 09-May-2007
Document revision history
Revision 1 Initial release Changes
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ST10F272M
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